Harman Kardon AVR 171 (serv.man3) Service Manual ▷ View online
Data Sheet: DM Series
DM860A Networked Media Processor
dat_DM860A_1_1_datasheet.doc
CONFIDENTIAL
Version 1.1 – July 11
th
2011 - Page 17 of 70
2.9 Serial Peripheral Interface (SPI)
Name
Pin
Type Description
SPIDIN
D14
I
SPI data receive
SPIDOUT
D15
O
SPI data transmit
SPICLK B16
I/O
SPI
clock
SPINCS0 C15
I/O
Multi-master mode:
chip-select input (used to detect bus conflict)
Master only mode:
chip-select 1 output
Slave mode:
chip-select input
SPINCS1 B17
I/O
Multi-master mode:
chip-select 2 output
Master only mode:
chip-select 2 output
Slave mode:
not used
Harman Kardon
AVR 171 Service Manual
Page 89 of 174
Data Sheet: DM Series
DM860A Networked Media Processor
dat_DM860A_1_1_datasheet.doc
CONFIDENTIAL
Version 1.1 – July 11
th
2011 - Page 18 of 70
2.10 External Memory Interface
Name
Pin(s)
Type Description
D[15:0]
T18, R18, P17,
P18, N15, N16,
N17, N18, M15,
M16, M17, M18,
L15, L16, L17, L18
P18, N15, N16,
N17, N18, M15,
M16, M17, M18,
L15, L16, L17, L18
I/O
Data bus for external memory and peripheral access
A[12:0]
E18, E17, E16,
E15, D18, D17,
D16, C18, C17,
C16, B18, A18,
A17
E15, D18, D17,
D16, C18, C17,
C16, B18, A18,
A17
O
Address bus for external memory and peripheral access
A13_RAS F15
O SRAM: address
output
SDRAM: row
access
strobe
A14_CAS F16
O SRAM: address
output
SDRAM: column access strobe
A15_BA0 F17
O
SRAM: address
output
SDRAM: bank
select
A16_BA1 F18
O
SRAM: address
output
SDRAM: bank
select
A17_DQM0 G15
O SRAM: address
output
SDRAM: data
mask
A18_DQM1 G16
O SRAM: address
output
SDRAM: data
mask
A[23:19]
H17, H16, H15,
G18, G17
G18, G17
O
Address bus for external memory and peripheral access
NCS[3:0]
H18, J17, J16, J15
O
Chip select signals. The active memory range for NCS[n]
(active low) can be configured.
(active low) can be configured.
NCS[0] supports SRAM, can be used for booting
NCS[1] supports SDRAM or SRAM
NCS[2] supports SRAM
NCS[3] supports SRAM
NCS[1] supports SDRAM or SRAM
NCS[2] supports SRAM
NCS[3] supports SRAM
NOE
K17
O
Output enable, asserted (low) for read operations
NWE
K16
O
Write enable, asserted (low) for write operations
NWAIT K18
I
External wait line. If NWAIT is asserted, memory access will
be stalled. Can be configured as either low-active (default) or
high-active.
be stalled. Can be configured as either low-active (default) or
high-active.
MEMCLK K15
O
SDRAM
system
clock
MEMCKE J18
O SDRAM
clock
enable
Harman Kardon
AVR 171 Service Manual
Page 90 of 174
Data Sheet: DM Series
DM860A Networked Media Processor
dat_DM860A_1_1_datasheet.doc
CONFIDENTIAL
Version 1.1 – July 11
th
2011 - Page 19 of 70
2.11 NAND-Flash Interface
Name
Pin(s)
Type Description
FD[7:0]
T17, T16, T15,
R17, R16, R15,
P16, P15
R17, R16, R15,
P16, P15
I/O
Bi-directional data bus
FALE
V18
O
Address latch enable;
pull-up/down defines boot mode
FCLE
U16
O
Command latch enable; pull-up/down defines boot mode
NFCE0 U15
O
Chip-enable,
low-active
NFRB
U18
I
Ready/busy. NAND flash is busy when NFRB is low.
NFRE
V17
O
Read enable, low-active
NFWE
U17
O
Write enable, low-active
NFWP
V16
O
Write protect, low-active
2.12 Ethernet MAC-Phy Interface (MII)
Name
Pin
Type
MII
RMII
SMII
MIIDIO
U14
I/O
management data
management data
MIIMDC
V14
O
management clock
management clock
MIIRXD[3]
V13
I
RxD 3
RxD 1
MIIRXD[2]
U13
I
RxD 2
RxD 0
MIIRXD[1] V12
I RxD
1
Rx-Sync
MIIRXD[0] U12
I RxD
0
RxD
MIIRXCLK T12
I receive
clock
receive
clock
MIIRXER
R13
I
receive error
receive error
MIIRXDV
T14
I
receive data valid
carrier sense/data valid
MIITXD[3]
V11
O
TxD 3
TxD 1
MIITXD[2]
U11
O
TxD 2
TxD 0
MIITXD[1] V10 O
TxD
1
Tx-Sync
MIITXD[0] U10 O
TxD
0
TxD
MIITXCLK R12
I transmit
clock
transmit
clock
MIITXER T11 O
transmit
error
MIITXEN
R11
O
transmit data enable
transmit data enable
MIICOL
T13
I
MII ethernet collision
MIICRS
R14
I
MII carrier sense
MIIPHYCLK V15
O 25.000
MHz
clock
50.000 MHz clock
125.000 MHz clock
Harman Kardon
AVR 171 Service Manual
Page 91 of 174
Data Sheet: DM Series
DM860A Networked Media Processor
dat_DM860A_1_1_datasheet.doc
CONFIDENTIAL
Version 1.1 – July 11
th
2011 - Page 20 of 70
2.13 USB 2.0 OTG
Name
Pin
Type Description
USBD+
B1
I/O
Positive data line that is connected to the serial USB cable
USBD–
A1
I/O
Negative data line that is connected to the serial USB cable
USBID
E2
I
USB ID pin of mini-AB receptacle
USBREXT
C2
I
External bias resistor (2K7, 1%); connect resistor to VSSUSB
USBVBUS
D2
I
VBUS voltage sense
USBVBUSDRV
E3
O
Control signal to control VBUS 5V voltage source
USBXTALI C4 I
Oscillator circuit input for a 24.000 MHz crystal (optional).
Without external crystal, pull this pin to GND.
Without external crystal, pull this pin to GND.
USBXTALO C3 O
Oscillator circuit output for a 24.000 MHz crystal (optional).
Without external crystal, leave this pin open.
Without external crystal, leave this pin open.
USBATST
D3
–
Do not connect
2.14 Power-on Reset Pins
Name
Pin
Type Description
NRES12REF D6
I
Voltage reference input. NRES12OUT is release when this input
voltage exceeds V
voltage exceeds V
TH12
.
NRES12OUT
C5
O
Open-drain reset (active low) for 1.2V core power supply.
NRES33REF D5
I
Voltage reference input. NRES33OUT is release when this input
voltage exceeds V
voltage exceeds V
TH33
.
NRES33OUT
D4
O
Open-drain reset (active low) for 3.3V core power supply
2.15 Real-Time Clock (RTC) Pins
Name
Pin
Type
Description
RTCXIN
F2
I
Oscillator circuit input. Connect 32.768 kHz tuning fork crystal here.
RTCXOUT
G2
O
Oscillator circuit output. Connect 32.768 kHz tuning fork crystal here.
VDD33RTC
F1
Power
Power supply (+3.3 V) for RTC
VSS33RTC
E1
Power
Ground (0 V) for RTC
Harman Kardon
AVR 171 Service Manual
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