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A3V28S30FTP   
A3V28S40FTP 

128M Single Data Rate Synchronous DRAM 

 

Revision 1.0                                                            Apr., 2010

Page 4 / 39 

 

 

CLK

Input

Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive 
edge of CLK. CLK also increments the internal burst counter and controls the output registers. 

CKE

Input

Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the 
clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), 
ACTIVE POWER-DOWN (row active in any bank), or CLOCK SUSPEND operation (burst/
access in progress). CKE is synchronous except after the device enters self refresh mode, where 
CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, 
are disabled duringself refresh mode, providing low standby power. CKE may be tied HIGH. 

/CS

Input

Chip Select: /CS enables (registered LOW) and disables (registered HIGH) the command 
decoder. All commands are masked when /CS is registered HIGH. /CS provides for external 
bank selection on systems with multiple banks. /CS is considered part of the command code. 

/CAS, 
/RAS, 

/WE

Input

Command Inputs: /CAS, /RAS, and /WE (along with /CS) define the command being entered. 

DQM, 

DQML, 

DQMU,

Input

Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and 
an output disable signal for read accesses. Input data is masked during a WRITE cycle. The 
output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. DQM 
corresponds to DQ0–DQ7(A3V28S30FTP). DQML corresponds to DQ0–DQ7, DQMU 
corresponds to DQ8–DQ15(A3V28S40FTP). 

BA0, BA1

Input

Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or 
PRECHARGE command is being applied. 

 

A0–A11

Input

A0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is 
specified by A0-11. The Column Address is specified by A0-9(x8) and A0-8(x16). A10 is also 
used to indicate precharge option. When A10 is high at a read / write command, an auto 
precharge is performed. When A10 is high at a precharge command, all banks are precharged. 
 

DQ0–DQ15

I/O

Data Input / Output: Data bus. 

NC

–

Internally Not Connected: These could be left unconnected, but it is recommended they be 
connected or V

SS

.

 

VddQ

Supply

Data Output Power: Provide isolated power to output buffers for improved noise immunity. 

VssQ

Supply

Data Output Ground: Provide isolated ground to output buffers for improved noise immunity. 

Vdd

Supply

Power for the input buffers and core logic. 

Vss

Supply

Ground for the input buffers and core logic. 

Harman Kardon

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Page 117 of 178

2005. 10. 26

1/4

Revision No : 1

INTERFACE AND SWITCHING APPLICATION. 

FEATURES

ESD Protected 2000V.

High density cell design for low R

DS(ON)

.

Voltage controlled small signal switch.

Rugged and reliable.

High saturation current capablity.

MAXIMUM RATING  (Ta=25

)

DIM

MILLIMETERS

1. SOURCE

2. GATE

3. DRAIN

SOT-23

A
B
C
D

E

2.93   0.20

1.30+0.20/-0.15

0.45+0.15/-0.05
2.40+0.30/-0.20

G

1.90

H

J

K

L

M

N

0.95

0.13+0.10/-0.05

0.00 ~ 0.10

0.55

0.20 MIN

1.00+0.20/-0.10

M

J

K

E

1

2

3

H

G

A

N

C

B

D

1.30 MAX

L

L

P

P

P

7

+_

ELECTRICAL CHARACTERISTICS  (Ta=25

)

CHARACTERISTIC

SYMBOL

TEST CONDITION

MIN.

TYP.

MAX.

UNIT

Drain-Source Breakdown Voltage

BV

DSS

V

GS

=0V,  I

D

=10 A

60

-

-

V

Zero Gate Voltage Drain Current

I

DSS

V

DS

=60V,  V

GS

=0V

-

-

1

A

Gate-Body Leakage, Forward

I

GSSF

V

GS

=20V,  V

DS

=0V

-

-

10

A

Gate-Body Leakage, Reverse

I

GSSR

V

GS

=-20V,  V

DS

=0V

-

-

-10

A

G

D

S

Type Name

Marking

Lot No.

WC

EQUIVALENT CIRCUIT

CHARACTERISTIC

SYMBOL

RATING

UNIT

Drain-Source Voltage 

V

DSS

60

V

Gate-Source Voltage

V

GSS

20

V

Drain Current

Continuous

I

D

300

mA

Pulsed

(Note 1)

I

DP

1200

Drain Power Dissipation 

(Note 2)

P

D

300

mW

Junction Temperature

T

j

150

Storage Temperature Range

T

stg

-55

150

Note 1) Pulse Width

10

,  Duty Cycle

1%

Note 2) Package mounted on a glass epoxy PCB(100mm

2

1mm)

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Page 118 of 178

©

1996

μ

 The 

μPA672T is a super-mini-mold device provided

with two MOS FET elements.  It achieves high-density

mounting and saves mounting costs.

•

Two MOS FET circuits in package the same size as

SC-70

•

Automatic mounting supported

PARAMETER

SYMBOL

TEST CONDITIONS

RATINGS

UNIT

Drain to Source Voltage

V

DSS

50

V

Gate to Source Voltage

V

GSS

±7.0

V

Drain Current (DC)

I

D(DC)

100

mA

Drain Current (pulse)

I

D(pulse)

PW

≤ 10 ms, Duty Cycle ≤ 50 %

200

mA

Total Power Dissipation

P

T

200 (Total)

mW

Channel Temperature

T

ch

150

˚C

Storage Temperature

T

stg

–55 to +150

˚C

Document No.  G11259EJ1V0DS00 (1st edition)
Date Published  June 1996 P
Printed in Japan

0.2

+0.1
–0

0.15

+0.1
–0.05

2.1 ±

0

.1

1.25 ±

0

.1

0.65

1.3

0.7

2.0 ±0.2

0.9 ±0.1

0 to 0.1

0.65

6

1

5

2

4

3

6

5

4

1

2

3

1.
2.
3.
4.
5.
6.
Marking:  MA

Source 1
Gate 1
Drain 2
Source 2
Gate 2
Drain 1

(S1)
(G1)
(D2)
(S2)
(G2)
(D1)

Harman Kardon

$95$956

6HUYLFH0DQXDO

6HUYLFH0DQXDO

Page 119 of 178

Harman Kardon

$95$956

6HUYLFH0DQXDO

6HUYLFH0DQXDO

Page 120 of 178