Harman Kardon AVR 161S (serv.man2) Service Manual ▷ View online
600mA LOW DROPOUT LINEAR REGULATOR
AP2317
600mA LOW DROPOUT LINEAR REGULATOR
AP1117M
Data Sheet
LOW DROPOUT LINEAR REGULATOR AZ1117C
2
Jan. 2012 Rev. 1. 5
BCD Semiconductor Manufacturing Limited
H Package
(SOT-223)
Pin Configuration
VOUT
INPUT
OUTPUT
ADJ/GND
1
2
3
Figure 2. Pin Configuration of AZ1117C (Top View)
D Package
(TO-252-2 (1))
1
2
3
1
2
3
INPUT
OUTPUT
ADJ/GND
INPUT
OUTPUT
ADJ/GND
INPUT
OUTPUT
ADJ/GND
(TO-252-2 (2))
(TO-252-2 (3))
1
2
3
R Package
(SOT-89)
1
2
3
INPUT
OUTPUT
ADJ/GND
VOUT
(TO-252-2 (4))
INPUT
OUTPUT
ADJ/GND
VOUT
1
2
3
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Page 113 of 178
2
3597Q–DFLASH–6/11
Atmel AT45DB321D
1.
Description
The Atmel AT45DB321D is a 2.5V or 2.7V, serial interface, sequential access flash memory ideally suited for a wide variety of
digital voice-, image-, program code-, and data-storage applications. The AT45DB321D supports the Atmel RapidS serial
interface for applications requiring very high speed operations. The RapidS serial interface is SPI compatible for frequencies up
to 66MHz. The 34,603,008-bits of memory are organized as 8,192 pages of 512 bytes or 528 bytes each. In addition to the main
memory, the AT45DB321D also contains two SRAM buffers of 512/528 bytes each. These buffers allow the receiving of data
while a page in the main memory is being reprogrammed, as well as the writing of a continuous data stream. EEPROM
(electrically erasable and programmable read-only memory) emulation (bit or byte alterability) is easily handled with a self-
contained, three-step read-modify-write operation. Unlike conventional flash memories, which are accessed randomly with
multiple address lines and a parallel interface, Atmel DataFlash
digital voice-, image-, program code-, and data-storage applications. The AT45DB321D supports the Atmel RapidS serial
interface for applications requiring very high speed operations. The RapidS serial interface is SPI compatible for frequencies up
to 66MHz. The 34,603,008-bits of memory are organized as 8,192 pages of 512 bytes or 528 bytes each. In addition to the main
memory, the AT45DB321D also contains two SRAM buffers of 512/528 bytes each. These buffers allow the receiving of data
while a page in the main memory is being reprogrammed, as well as the writing of a continuous data stream. EEPROM
(electrically erasable and programmable read-only memory) emulation (bit or byte alterability) is easily handled with a self-
contained, three-step read-modify-write operation. Unlike conventional flash memories, which are accessed randomly with
multiple address lines and a parallel interface, Atmel DataFlash
®
devices use a RapidS serial interface to sequentially access its
data. The simple sequential access dramatically reduces active pin count, facilitates hardware layout, increases system
reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and
industrial applications where high density, low pin count, low voltage and low power are essential.
reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and
industrial applications where high density, low pin count, low voltage and low power are essential.
To allow for simple, in-system reprogrammability, the AT45DB321D does not require high input voltages for programming. The
device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB321D is
enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the serial input (SI), serial output
(SO), and serial clock (SCK) lines.
device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB321D is
enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the serial input (SI), serial output
(SO), and serial clock (SCK) lines.
All programming and erase cycles are self timed.
Figure 1-1.
Pin configurations and pinouts.
MLF
(1)
(VDFN)
Top View
Note:
1.
The metal pad on the bottom of
the MLF package is floating.
This pad can be a “No Connect” or
connected to GND.
the MLF package is floating.
This pad can be a “No Connect” or
connected to GND.
SOIC
Top View
BGA Package Ball-out
Top View
TSOP: Type 1
Top View
Note:
TSOP package is not recommended for new designs.
Future die shrinks will support 8-pin packages only.
Future die shrinks will support 8-pin packages only.
SI
SCK
RESET
CS
SO
GND
VCC
WP
GND
VCC
WP
8
7
6
5
7
6
5
1
2
3
4
2
3
4
1
2
3
4
2
3
4
8
7
6
5
7
6
5
SI
SCK
RESET
CS
SO
GND
VCC
WP
GND
VCC
WP
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCC
GND
SCK
CS RDY/BSY WP
SI
SO
RESET
1 2
3
4
5
A
B
C
D
E
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RDY/BUSY
RESET
WP
NC
NC
VCC
GND
NC
NC
NC
CS
SCK
SI
SO
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
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3
3597Q–DFLASH–6/11
Atmel AT45DB321D
Table 1-1.
Pin Configurations
Symbol
Name and Function
Asserted
State
Type
CS
Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in the standby mode (not deep power-
down mode), and the output pin (SO) will be in a high-impedance state. When the device
is deselected, data will not be accepted on the input pin (SI).
device will be deselected and normally be placed in the standby mode (not deep power-
down mode), and the output pin (SO) will be in a high-impedance state. When the device
is deselected, data will not be accepted on the input pin (SI).
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation
such as a program or erase cycle, the device will not enter the standby mode until the
completion of the operation.
transition is required to end an operation. When ending an internally self-timed operation
such as a program or erase cycle, the device will not enter the standby mode until the
completion of the operation.
Low
Input
SCK
Serial Clock: This pin is used to provide a clock to the device, and is used to control the
flow of data to and from the device. Command, address, and input data present on the SI
pin are always latched on the rising edge of SCK, while output data on the SO pin are
always clocked out on the falling edge of SCK.
flow of data to and from the device. Command, address, and input data present on the SI
pin are always latched on the rising edge of SCK, while output data on the SO pin are
always clocked out on the falling edge of SCK.
–
Input
SI
Serial Input: The SI pin is used to shift data into the device. The SI pin is used for all data
input, including command and address sequences. Data on the SI pin are always latched
on the rising edge of SCK.
input, including command and address sequences. Data on the SI pin are always latched
on the rising edge of SCK.
–
Input
SO
Serial Output: The SO pin is used to shift data out from the device. Data on the SO pin
are always clocked out on the falling edge of SCK.
are always clocked out on the falling edge of SCK.
–
Output
WP
Write Protect: When the WP pin is asserted, all sectors specified for protection by the
sector protection register will be protected against program and erase operations,
regardless of whether the enable sector protection command has been issued or not. The
WP pin functions independently of the software controlled protection method. After the
WP pin goes low, the content of the sector protection register cannot be modified.
sector protection register will be protected against program and erase operations,
regardless of whether the enable sector protection command has been issued or not. The
WP pin functions independently of the software controlled protection method. After the
WP pin goes low, the content of the sector protection register cannot be modified.
If a program or erase command is issued to the device while the WP pin is asserted, the
device will simply ignore the command and perform no operation. The device will return to
the idle state once the CS pin has been deasserted. The enable sector protection
command and sector lockdown command, however, will be recognized by the device
when the WP pin is asserted.
device will simply ignore the command and perform no operation. The device will return to
the idle state once the CS pin has been deasserted. The enable sector protection
command and sector lockdown command, however, will be recognized by the device
when the WP pin is asserted.
The WP pin is internally pulled high, and may be left floating if hardware controlled
protection will not be used. However, it is recommended that the WP pin also be
externally connected to V
protection will not be used. However, it is recommended that the WP pin also be
externally connected to V
CC
whenever possible.
Low
Input
RESET
Reset: A low state on the reset pin (RESET) will terminate the operation in progress and
reset the internal state machine to an idle state. The device will remain in the reset
condition as long as a low level is present on the RESET pin. Normal operation can
resume once the RESET pin is brought back to a high level.
reset the internal state machine to an idle state. The device will remain in the reset
condition as long as a low level is present on the RESET pin. Normal operation can
resume once the RESET pin is brought back to a high level.
The device incorporates an internal power-on reset circuit, and so there are no restrictions
on the RESET pin during power-on sequences. If this pin and feature are not utilized, it is
recommended that the RESET pin be driven high externally.
on the RESET pin during power-on sequences. If this pin and feature are not utilized, it is
recommended that the RESET pin be driven high externally.
Low
Input
RDY/BUSY
Ready/Busy: This open drain output pin will be driven low when the device is busy in an
internally self-timed operation. This pin, which is normally in a high state (through
an external pull-up resistor), will be pulled low during programming/erase operations,
compare operations, and page-to-buffer transfers.
internally self-timed operation. This pin, which is normally in a high state (through
an external pull-up resistor), will be pulled low during programming/erase operations,
compare operations, and page-to-buffer transfers.
The busy status indicates that the flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed.
accessed; read and write operations to the other buffer can still be performed.
–
Output
V
CC
Device Power Supply: The V
CC
pin is used to supply the source voltage to the device.
Operations at invalid V
CC
voltages may produce spurious results and should not be
attempted.
–
Power
GND
Ground: The ground reference for the power supply. GND should be connected to the
system ground.
system ground.
–
Ground
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Page 115 of 178
A3V28S30FTP
A3V28S40FTP
A3V28S40FTP
128M Single Data Rate Synchronous DRAM
Revision 1.0 Apr., 2010
Page 2 / 39
CLK
: Master Clock
DQM : Output Disable / Write Mask(A3V28S30FTP)
CKE
: Clock Enable
DQMU,L : Output Disable / Write Mask(A3V28S40FTP)
/CS
:
Chip
Select A0-11
:
Address
Input
/RAS
:
Row
Address
Strobe
BA0,1
:
Bank
Address
/CAS
: Column Address Strobe
Vdd : Power Supply
/WE
:
Write
Enable
VddQ
:
Power
Supply
for
Output
DQ0-7
: Data I/O (A3V28S30FTP)
Vss : Ground
DQ0-15
: Data I/O (A3V28S40FTP)
VssQ : Ground for Output
BA0
BA1
Vdd
DQ0
VddQ
DQ1
DQ2
VssQ
DQ3
DQ4
VddQ
DQ5
DQ6
VssQ
DQ7
Vdd
DQML
/WE
/CAS
/RAS
/CS
A10(AP)
A2
A3
Vdd
A0
A1
Vdd
DQ0
VddQ
NC
DQ1
VssQ
NC
DQ2
VddQ
NC
DQ3
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10(AP)
A2
A3
Vdd
A0
A1
DQM
CKE
Vss
DQ15
VssQ
DQ14
DQ13
VddQ
DQ12
DQ15
VssQ
DQ14
DQ13
VddQ
DQ12
DQ11
VssQ
DQ10
DQ9
VddQ
DQ8
Vss
NC
DQMU
CLK
CKE
NC
VssQ
DQ10
DQ9
VddQ
DQ8
Vss
NC
DQMU
CLK
CKE
NC
A11
A8
A7
A6
A5
A4
Vss
A7
A6
A5
A4
Vss
A9
Vss
DQ7
VssQ
NC
DQ6
VddQ
NC
DQ5
VssQ
NC
DQ4
VddQ
NC
Vss
NC
CLK
NC
A11
A8
A7
A6
A5
A4
Vss
A9
PIN CONFIGURATION (TOP VIEW)
PIN CONFIGURATION
(TOP VIEW)
x8
x16
1
2
3
4
5
6
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
9
10
11
12
13
14
15
16
17
18
19
20
21
22
21
22
54
53
52
51
50
49
48
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
46
45
44
43
42
41
40
39
38
37
36
35
34
33
34
33
23
32
24
31
25
30
26
29
27
28
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