Harman Kardon AVR 151S Service Manual ▷ View online
ML61
Packaging Information
Recommended Pattern Layout
0.4
-0.1
-0.05
-0.05
(0.95)
1.9
r 0.2
2.9
r 0.2
1.6
-0
.0
.1
+1
.2
2.
8
r 0.
2
1.1
r 0.1
mi
n.
0.
2
0 ~ 0.1
(0.8)
0.15
-0.1
-0.05
-0.05
1.5
r 0.1
1.5
r 0.1
0.49
r 0.06
0.42
r 0.06
0.42
r 0.06
2.45
r
0.1
5
4.25
m
ax
1.72
r 0.1
4.5
r 0.1
1.1 m
m
0.4
r 0.04
1.5
r 0.1
SOT-89 :
SOT-23 :
4.
2 m
ax
1.27 1.27
5.2 max
5.
3 m
ax
12
.7
m
in
TO-92 :
Units : mm
SOT-89
SOT-23 :
0.
9
1.
5
1.6
1.0
1. 0
3.
7
45º
45º
2.2
P10/14
0.
8
1.0
1.
9
2.4
Harman Kardon
Page 97 of 131
Harman Kardon
Page 98 of 131
July 2006
Rev 8
1/34
1
M24C64-W M24C64-R M24C64-F
M24C32-W M24C32-R M24C32-F
M24C32-W M24C32-R M24C32-F
64 Kbit and 32 Kbit Serial I²C bus EEPROM
Feature summary
■
Two-Wire I
2
C serial interface
Supports 400kHz Protocol
■
Single supply voltage:
– 2.5 to 5.5V for M24Cxx-W
– 1.8 to 5.5V for M24Cxx-R
– 1.7 to 5.5V for M25Cxx-F
■
Write Control Input
■
Byte and Page Write (up to 32 Bytes)
■
Random And Sequential Read modes
■
Self-Timed programming cycle
■
Automatic address incrementing
■
Enhanced ESD/Latch-Up Protection
■
More than 1 Million Write cycles
■
More than 40-year data retention
PDIP8 (BN)
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
UFDFPN8 (MB)
2x3mm² (MLP)
www.st.com
Harman Kardon
Page 99 of 131
Summary description
M24Cxx-W, M24Cxx-R, M24Cxx-F
6/34
1 Summary
description
These I
2
C-compatible electrically erasable programmable memory (EEPROM) devices are
organized as 8192 × 8 bits (M24C64-x) and 4096 × 8 bits (M24C32-x).
Figure 1.
Logic diagram
I
2
C uses a two-wire serial interface, comprising a bi-directional data line and a clock line.
The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the
I
I
2
C bus definition.
The device behaves as a slave in the I
2
C protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a Device Select Code and Read/Write
bit (RW) (as described in
by the bus master. The Start condition is followed by a Device Select Code and Read/Write
bit (RW) (as described in
Table 2
), terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9
th
bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
Table 1.
Signal names
E0, E1, E2
Chip Enable
SDA
Serial Data
SCL
Serial Clock
WC
Write Control
V
CC
Supply Voltage
V
SS
Ground
AI01844c
3
E0-E2
SDA
VCC
M24C64-W
M24C64-R
M24C64-F
M24C32-W
M24C32-R
M24C32-F
WC
SCL
VSS
Harman Kardon
Page 100 of 131
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