Harman Kardon AVR 151S Service Manual ▷ View online
M24Cxx-W, M24Cxx-R, M24Cxx-F
Summary description
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Figure 2.
DIP, SO, TSSOP and UFDFPN connections
1.
See
Package mechanical
section for package dimensions, and how to identify pin-1.
SDA
VSS
SCL
WC
E1
E0
VCC
E2
AI01845d
M24C64-x
M24C32-x
M24C32-x
1
2
3
4
8
7
6
5
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Signal description
M24Cxx-W, M24Cxx-R, M24Cxx-F
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2 Signal
description
2.0.1
Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor must be connected from Serial Clock
(SCL) to V
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor must be connected from Serial Clock
(SCL) to V
CC
. (
Figure 4
indicates how the value of the pull-up resistor can be calculated). In
most applications, though, this method of synchronization is not employed, and so the pull-
up resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
up resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.0.2
Serial Data (SDA)
This bi-directional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to V
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to V
CC
. (
Figure 4
indicates how
the value of the pull-up resistor can be calculated).
2.1
Chip Enable (E0, E1, E2)
These input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs must be tied to
V
significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs must be tied to
V
CC
or V
SS
, to establish the Device Select Code as shown in
Figure 3
. When not connected
(left floating), these inputs are read as Low (0,0,0).
Figure 3.
Device select code
2.2
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven High. When unconnected, the signal is internally read as V
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven High. When unconnected, the signal is internally read as V
IL
, and
Write operations are allowed.
When Write Control (WC) is driven High, Device Select and Address bytes are
acknowledged, Data bytes are not acknowledged.
acknowledged, Data bytes are not acknowledged.
Ai12806
VCC
M24xxx
VSS
Ei
VCC
M24xxx
VSS
Ei
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M24Cxx-W, M24Cxx-R, M24Cxx-F
Signal description
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2.3
Supply voltage (V
CC
)
2.3.1
Operating supply voltage V
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V
CC
voltage
within the specified [V
CC
(min), V
CC
(max)] range must be applied (see
Table 8
and
Table 9
).
In order to secure a stable DC supply voltage, it is recommended to decouple the V
CC
line
with a suitable capacitor (usually of the order of 10nF to 100nF) close to the V
CC
/V
SS
package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (t
and, for a Write instruction, until the completion of the internal write cycle (t
W
).
2.3.2
Internal device reset
In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR)
circuit is included. At Power-up (continuous rise of V
circuit is included. At Power-up (continuous rise of V
CC
), the device does not respond to any
instruction until V
CC
has reached the Power On Reset threshold voltage (this threshold is
lower than the minimum V
CC
operating voltage defined in
Table 8
and
Table 9
).
When V
CC
has passed the POR threshold, the device is reset and is in Standby Power
mode.
2.3.3 Power-down
At Power-down (continuous decrease of V
CC
), as soon as V
CC
drops from the normal
operating voltage to below the Power On Reset threshold voltage, the device stops
responding to any instruction sent to it.
responding to any instruction sent to it.
During Power-down, the device must be deselected and in the Standby Power mode (that is
there should be no internal Write cycle in progress).
there should be no internal Write cycle in progress).
Figure 4.
Maximum R
P
value versus bus parasitic capacitance (C) for an I
2
C bus
AI01665b
VCC
C
SDA
R
P
MASTER
R
P
SCL
C
100
0
4
8
12
16
20
C (pF)
Maximum RP value (k
Ω
)
10
1000
fc = 400kHz
fc = 100kHz
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Signal description
M24Cxx-W, M24Cxx-R, M24Cxx-F
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Figure 5.
I
2
C bus protocol
Table 2.
Device select code
Device Type Identifier
(1)
1.
The most significant bit, b7, is sent first.
Chip Enable Address
(2)
2.
E0, E1 and E2 are compared against the respective external pins on the memory device.
RW
b7
b6
b5
b4
b3
b2
b1
b0
Device Select Code
1
0
1
0
E2
E1
E0
RW
Table 3.
Address Most Significant Byte
b15
b14
b13
b12
b11
b10
b9
b8
Table 4.
Address Least Significant Byte
b7
b6
b5
b4
b3
b2
b1
b0
SCL
SDA
SCL
SDA
SDA
START
Condition
SDA
Input
SDA
Change
AI00792B
STOP
Condition
1
2
3
7
8
9
MSB
ACK
START
Condition
SCL
1
2
3
7
8
9
MSB
ACK
STOP
Condition
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