Harman Kardon AVR 151S Service Manual ▷ View online
ADI Confidential
ADV7623
Rev. Sp0 | Page 11 of 16
Pin No. Mnemonic
Type
Description
56 TX2−
HDMI
output Differential Output Channel 2 Complement. Differential output of the red data at 10×
the pixel clock rate; supports TMDS logic level.
57 TX2+
HDMI
output Differential Output Channel 2 True. Differential output of the red data at 10× the pixel
clock rate; supports TMDS logic level.
58 TXGND Ground
TXAVDD
Ground.
59
CEC
Digital I/O
Consumer Electronics Control Channel (5 V Tolerant).
60 DGND Ground
DVDD
Ground.
61
DVDD
Power
Digital Supply Voltage (1.8 V).
62
ALSB
Digital input
This pin is used to set the I
2
C address of the Rx IO and the Tx main map.
63
CS
Digital input
Chip Select Pin. This pin must be set low or left floating for the chip to process I
2
C messages
that are destined for the ADV7623. The ADV7623 ignores I
2
C messages that it receives if
this pin is high.
64
EP_SCK
Digital output
SPI Clock Interface for the EDID/OSD.
65
EP_CS
Digital output
SPI Chip Selected Interface for the EDID/OSD.
66
EP_MOSI
Digital output
SPI Master Out/Slave In for the EDID/OSD.
67
EP_MISO
Digital input
SPI Master In/Slave Out for the EDID/OSD.
68 MCLK_IN
Digital
input Audio Reference Clock. 128 × N × f
S
with N = 1, 2, 3, or 4. Set to 128 × sampling frequency (f
S
),
256 × f
S
, 384 × f
S
, or 512 × f
S
. It supports CMOS logic levels from 1.8 V to 3.3 V.
69 SCLK_IN Digital
input I
2
S Audio Clock. It supports CMOS logic levels from 1.8 V to 3.3 V.
70
AP5_IN
Digital input
Audio Input Port 5. It supports CMOS logic levels from 1.8 V to 3.3 V.
71
AP4_IN
Digital input
Audio Input Port 4. It supports CMOS logic levels from 1.8 V to 3.3 V.
72 DGNDIO Ground
DVDDIO
Ground.
73
DVDDIO
Power
Digital I/O Supply Voltage (3.3 V).
74
AP3_IN
Digital input
Audio Input Port 3. It supports CMOS logic levels from 1.8 V to 3.3 V.
75
AP2_IN
Digital input
Audio Input Port 2. It supports CMOS logic levels from 1.8 V to 3.3 V.
76
AP1_IN
Digital input
Audio Input Port 1. It supports CMOS logic levels from 1.8 V to 3.3 V.
77
AP0_IN
Digital input
Audio Input Port 0. It supports CMOS logic levels from 1.8 V to 3.3 V.
78 SDATA Digital
I/O I
2
C Port Serial Data Input/Output Pin. SDATA is the data line for the control port.
79 SCL
Digital
input I
2
C Port Serial Clock Input. SCL is the clock line for the control port.
80 DGND Ground
DVDD
Ground.
81
DVDD
Power
Digital Supply Voltage (1.8 V).
82
INT1
(AMUTE1)
(AMUTE1)
Digital output
Interrupt Pin. This pin can be active low or active high. When status bits change, this pin is
triggered. The events that trigger an interrupt are under user control. This pin can also output
an audio mute signal.
triggered. The events that trigger an interrupt are under user control. This pin can also output
an audio mute signal.
83
INT2
(AMUTE2)
(AMUTE2)
Digital output
Interrupt Pin. This pin can be active low or active high. When status bits change, this pin is
triggered. The events that trigger an interrupt are under user control. This pin can also output
an audio mute signal.
triggered. The events that trigger an interrupt are under user control. This pin can also output
an audio mute signal.
84
INT_TX
Digital output
Interrupt; Open Drain. A 2 kΩ pull-up resistor to the microcontroller I/O supply is recommended.
85 DGNDIO
Ground
DVDDIO
Ground.
86
DVDDIO
Power
Digital I/O Supply Voltage (3.3 V).
87
AP0_OUT
Digital output
Audio Output Port 0.
88
AP1_OUT
Digital output
Audio Output Port 1.
89
AP2_OUT
Digital output
Audio Output Port 2.
90
AP3_OUT
Digital output
Audio Output Port 3.
91
AP4_OUT
Digital output
Audio Output Port 4.
92
DGND
Ground
DVDD Ground.
93
DVDD
Power
Digital Supply Voltage (1.8 V).
94
AP5_OUT
Digital output
Audio Output Port 5.
95
SCLK_OUT
Digital output
Audio Serial Clock Output.
96
MCLK_OUT
Digital output
Audio Master Clock Output.
97
RESET
Digital input
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7623 circuitry.
the ADV7623 circuitry.
98
PWRDN
Digital input
Active Low Power-Down Pin. If used, this pin should be pulled high to power up the
ADV7623. This pin can also be used as an in system power detect where internal EDID can
be powered from a 5 V signal of the HDMI port when it is connected to active equipment.
ADV7623. This pin can also be used as an in system power detect where internal EDID can
be powered from a 5 V signal of the HDMI port when it is connected to active equipment.
am Elect
S Aud
ud
Audio Input
o Input
Audio Input Po
o Input Po
e
DVDDIO Grou
DVDDIO G
e
Digital I/O S
Digital I/O
e
t
t
Audio Inp
Audio Inp
le
put
ut
Audio I
Audio
Ele
nput
nput
Audio
Audi
Ele
l input
l input
Aud
Aud
El
tal I/O
tal I/O
I
I
2
2
C
E
gital input
tal input
E
Ground
Power
Digital output
Digital o
m
TE2)
Digital ou
Digital o
am
T_TX
X
Digi
Digi
am
NDIO
DIO
Gr
Gr
a
P
aa
March 18,
tage (3.3
age
t supports CM
t supports CM
2. It supports CM
t supports
t 1. It supports C
1. It suppor
ort 0. It support
0. It supp
al Data Input/Ou
rial Clock Input.
Clo
round.
ound.
Supply Voltage
pply Volt
rupt Pin. This pi
pt Pin. This
ggered. The even
ed. The e
n audio mute sig
udio mute
Interrupt Pin. T
errupt P
triggered. The
riggered. T
an audio mu
an audio
Interrupt; O
Interrup
M
DVDDIO
DVD
M
Digita
Di
M
t
t
Aud
A
M
Au
M
DI Confid
gic leve
gic lev
ogic levels fro
ogic levels fro
n. SDAT
. SDAT
A is the data
A is the dat
T
T
T
he clock line for th
clock line for th
active low or acti
ve low or acti
trigger an interrup
r an interru
an be active low o
e active low
that trigger an inte
rigger an in
al.
ain. A 2 kΩ pull
ain. A 2 kΩ pull
-up r
up
.
ply Voltage (3.3 V)
y Voltage (3.3 V)
ut Port 0.
0.
put Port 1.
utput Port 2.
utput P
Output Port 3.
utput Port 3
o Output Port 4.
Output Port 4.
Ground.
Ground.
y Volta
y Vo
Harman Kardon
Page 73 of 131
ADV7623
ADI Confidential
Rev. Sp0 | Page 12 of 16
Pin No. Mnemonic
Type
Description
99 PGND Ground
PVDD
Ground.
100
PVDD
Power
PLL Supply Voltage (1.8 V).
101 XTAL
Miscellaneous
analog
analog
Input pin for 28.63636 MHz crystal or an external 1.8 V 28.63636 MHz clock oscillator source to
clock the ADV7623.
clock the ADV7623.
102 XTAL1
Miscellaneous
analog
analog
Crystal Output Pin. This pin should be left floating if a clock oscillator is used.
103
PVDD
Power
PLL Supply Voltage (1.8 V).
104 PGND
Ground
PVDD
Ground.
105
HP_CTRLA
Digital output
Hot Plug Detect for Port A.
106
5V_DETA
Digital input
5 V Detect Pin for Port A in the HDMI Interface.
107 RTERM Miscellaneous
analog
This pin sets the internal termination resistance. A 500 Ω resistor between this pin and
ground should be used.
ground should be used.
108
DDCA_SDA
Digital I/O
HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input/output that is 5 V tolerant.
109
DDCA_SCL
Digital input
HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant.
110
CVDD
Power
Receiver Comparator Supply Voltage (1.8 V).
111
CGND
Ground
TVDD and CVDD Ground.
112
RXA_C−
HDMI input
Digital Input Clock Complement of Port A in the HDMI Interface.
113
RXA_C+
HDMI input
Digital Input Clock True of Port A in the HDMI Interface.
114
TVDD
Power
Receiver Terminator Supply Voltage (3.3 V).
115
RXA_0−
HDMI input
Digital Input Channel 0 Complement of Port A in the HDMI Interface.
116
RXA_0+
HDMI input
Digital Input Channel 0 True of Port A in the HDMI Interface.
117
CGND
Ground
TVDD and CVDD Ground.
118
RXA_1−
HDMI input
Digital Input Channel 1 Complement of Port A in the HDMI Interface.
119
RXA_1+
HDMI input
Digital Input Channel 1 True of Port A in the HDMI Interface.
120
TVDD
Power
Receiver Terminator Supply Voltage (3.3 V).
121
RXA_2−
HDMI input
Digital Input Channel 2 Complement of Port A in the HDMI Interface.
122
RXA_2+
HDMI input
Digital Input Channel 2 True of Port A in the HDMI Interface.
123
HP_CTRLB
Digital output
Hot Plug Detect for Port B.
124
5V_DETB
Digital input
5 V Detect Pin for Port B in the HDMI Interface.
125 DGND
Ground
DVDD
Ground.
126
DVDD
Power
Digital Supply Voltage (1.8 V).
127
DDCB_SDA
Digital I/O
HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input/output that is 5 V tolerant.
128
DDCB_SCL
Digital input
HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant.
129
CVDD
Power
Receiver Comparator Supply Voltage (1.8 V).
130
CGND
Ground
TVDD and CVDD Ground.
131
RXB_C−
HDMI input
Digital Input Clock Complement of Port B in the HDMI Interface.
132
RXB_C+
HDMI input
Digital Input Clock True of Port B in the HDMI Interface.
133
TVDD
Power
Receiver Terminator Supply Voltage (3.3 V).
134
RXB_0−
HDMI input
Digital Input Channel 0 Complement of Port B in the HDMI Interface.
135
RXB_0+
HDMI input
Digital Input Channel 0 True of Port B in the HDMI Interface.
136
CGND
Ground
TVDD and CVDD Ground.
137
RXB_1−
HDMI input
Digital Input Channel 1 Complement of Port B in the HDMI Interface.
138
RXB_1+
HDMI input
Digital Input Channel 1 True of Port B in the HDMI Interface.
139
TVDD
Power
Receiver Terminator Supply Voltage (3.3 V).
140
RXB_2−
HDMI input
Digital Input Channel 2 Complement of Port B in the HDMI Interface.
141
RXB_2+
HDMI input
Digital Input Channel 2 True of Port B in the HDMI Interface.
142
HP_CTRLC
Digital output
Hot Plug Detect for Port C.
143
5V_DETC
Digital input
5 V Detect Pin for Port C in the HDMI Interface.
144
DDCC_SDA
Digital I/O
HDCP Slave Serial Data Port C. DDCC_SDA is a 3.3 V input/output that is 5 V tolerant.
am Elect
iver Term
Term
gital Input Chann
put Chann
Digital Input Chann
l Input Chann
TVDD and CVDD
DD and CVD
Digital Input Ch
gital Input C
Digital Input C
Digital Input C
l
Receiver Ter
Receive
El
Digital Inp
igital In
El
ut
ut
Digital I
Digital I
El
utput
utput
Hot Pl
Hot P
E
input
ut
5 V D
5 V
E
nd
DV
DV
E
wer
Digital I/O
al I/O
Digital input
ital input
Power
ower
Ground
Ground
HDMI inpu
HDMI inp
a
+
HDMI inp
HDMI inp
a
Power
Power
a
HDM
DM
a
March 18,
omplemen
omplemen
True of Port A in
rue of Port A i
upply Voltage (3
upply Voltage
el 2 Complemen
2 Comp
nel 2 True of Po
2 True of
for Port B.
for Port B in the
Port
d.
d.
pply Voltage (1.8
y Voltage
ve Serial Data P
Serial D
Slave Serial Cloc
ve Serial C
ver Comparato
Comp
DD and CVDD G
and CVDD
Digital Input Cloc
al Input C
Digital Input Cl
Digital Inpu
Receiver Term
Receiver T
M
Digital Inpu
Digital
M
Digital In
Digita
M
DD a
D
DI Confid
t A in the
A in the
e HDMI Interface
e HDMI Interfac
terface.
ace.
DCB_SDA is a 3.3 V
_SDA is a 3.3 V
DDCB_SCL is a 3.3
SCL is a 3.
Voltage (1.8 V).
age (1.8 V)
lement of Port B in
ment of Port B in
e of Port B in the HD
e of Port B in the H
Supply Voltage (3.3
upply Voltage (
el 0 Complement
0 Complement
nnel 0 True of Port
True of Port
D Ground.
Channel 1 Comple
Chann
t Channel 1 True o
Channel 1 Tr
erminator Supply V
rminator Supply
t Channel 2 Co
t Channel 2 Co
nnel 2 T
nnel
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