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 2

3597Q–DFLASH–6/11

 Atmel AT45DB321D

The Atmel AT45DB321D is a 2.5V or 2.7V, serial interface, sequential access flash memory ideally suited for a wide variety of
digital voice-, image-, program code-, and data-storage applications. The AT45DB321D supports the Atmel RapidS serial
interface for applications requiring very high speed operations. The RapidS serial interface is SPI compatible for frequencies up
to 66MHz. The 34,603,008-bits of memory are organized as 8,192 pages of 512 bytes or 528 bytes each. In addition to the main
memory, the AT45DB321D also contains two SRAM buffers of 512/528 bytes each. These buffers allow the receiving of data
while a page in the main memory is being reprogrammed, as well as the writing of a continuous data stream. EEPROM
(electrically erasable and programmable read-only memory) emulation (bit or byte alterability) is easily handled with a self-
contained, three-step read-modify-write operation. Unlike conventional flash memories, which are accessed randomly with
multiple address lines and a parallel interface, Atmel DataFlash

®

 devices use a RapidS serial interface to sequentially access its

data. The simple sequential access dramatically reduces active pin count, facilitates hardware layout, increases system
reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and
industrial applications where high density, low pin count, low voltage and low power are essential.

To allow for simple, in-system reprogrammability, the AT45DB321D does not require high input voltages for programming. The
device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB321D is
enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the serial input (SI), serial output
(SO), and serial clock (SCK) lines.

All programming and erase cycles are self timed.

Pin configurations and pinouts.

MLF

(1)

 (VDFN) 

Top View

Note:

1.

The metal pad on the bottom of 
the MLF package is floating.
This pad can be a “No Connect” or 
connected to GND.

SOIC 

Top View

BGA Package Ball-out 

Top View

TSOP: Type 1

Top View

Note:

TSOP package is not recommended for new designs.
Future die shrinks will support 8-pin packages only.

SI

SCK

RESET

CS

SO
GND
VCC
WP

8
7
6
5

1
2
3
4

1
2
3
4

8
7
6
5

SI

SCK

RESET

CS

SO
GND
VCC
WP

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

VCC

GND

SCK

CS RDY/BSY WP

SI

SO

RESET

 1  2 

3 

4 

5

A

B

C

D

E

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RDY/BUSY

RESET

WP

NC

NC

VCC

GND

NC

NC

NC

CS

SCK

SI

SO

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

Harman Kardon

Page 69 of 131

 3

3597Q–DFLASH–6/11

 Atmel AT45DB321D

CS

Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the 
device will be deselected and normally be placed in the standby mode (not deep power-
down mode), and the output pin (SO) will be in a high-impedance state. When the device 
is deselected, data will not be accepted on the input pin (SI).

A high-to-low transition on the CS pin is required to start an operation, and a low-to-high 
transition is required to end an operation. When ending an internally self-timed operation 
such as a program or erase cycle, the device will not enter the standby mode until the 
completion of the operation.

Low

Input

SCK

Serial Clock: This pin is used to provide a clock to the device, and is used to control the 
flow of data to and from the device. Command, address, and input data present on the SI 
pin are always latched on the rising edge of SCK, while output data on the SO pin are 
always clocked out on the falling edge of SCK.

–

Input

SI

Serial Input: The SI pin is used to shift data into the device. The SI pin is used for all data 
input, including command and address sequences. Data on the SI pin are always latched 
on the rising edge of SCK.

–

Input

SO

Serial Output: The SO pin is used to shift data out from the device. Data on the SO pin 
are always clocked out on the falling edge of SCK.

–

Output

WP

Write Protect: When the WP pin is asserted, all sectors specified for protection by the 
sector protection register will be protected against program and erase operations, 
regardless of whether the enable sector protection command has been issued or not. The 
WP pin functions independently of the software controlled protection method. After the 
WP pin goes low, the content of the sector protection register cannot be modified.

If a program or erase command is issued to the device while the WP pin is asserted, the 
device will simply ignore the command and perform no operation. The device will return to 
the idle state once the CS pin has been deasserted. The enable sector protection 
command and sector lockdown command, however, will be recognized by the device 
when the WP pin is asserted.

The WP pin is internally pulled high, and may be left floating if hardware controlled 
protection will not be used. However, it is recommended that the WP pin also be 
externally connected to V

CC

 whenever possible.

Low

Input

RESET

Reset: A low state on the reset pin (RESET) will terminate the operation in progress and 
reset the internal state machine to an idle state. The device will remain in the reset 
condition as long as a low level is present on the RESET pin. Normal operation can 
resume once the RESET pin is brought back to a high level.

The device incorporates an internal power-on reset circuit, and so there are no restrictions 
on the RESET pin during power-on sequences. If this pin and feature are not utilized, it is 
recommended that the RESET pin be driven high externally.

Low

Input

RDY/BUSY

Ready/Busy: This open drain output pin will be driven low when the device is busy in an 
internally self-timed operation. This pin, which is normally in a high state (through 
an external pull-up resistor), will be pulled low during programming/erase operations, 
compare operations, and page-to-buffer transfers.

The busy status indicates that the flash memory array and one of the buffers cannot be 
accessed; read and write operations to the other buffer can still be performed.

–

Output

V

CC

Device Power Supply: The V

CC

 pin is used to supply the source voltage to the device.

Operations at invalid V

CC

 voltages may produce spurious results and should not be 

attempted.

–

Power

GND

Ground: The ground reference for the power supply. GND should be connected to the 
system ground.

–

Ground

Harman Kardon

Page 70 of 131

ADI Confidential 

ADV7623

Rev. Sp0 | Page 9 of 16 

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 

0

83

02

-0

05

1 

DDCC_SCL 

Digital input 

HDCP Slave Serial Clock Port C. DDCC_SCL is a 3.3 V input that is 5 V tolerant. 

2 

CVDD 

Power 

Receiver Comparator Supply Voltage (1.8 V). 

3 

CGND 

Ground 

TVDD and CVDD Ground. 

4 

RXC_C− 

HDMI input 

Digital Input Clock Complement of Port C in the HDMI Interface. 

5 

RXC_C+ 

HDMI input 

Digital Input Clock True of Port C in the HDMI Interface. 

6 

TVDD 

Power 

Receiver Terminator Supply Voltage (3.3 V). 

7 

RXC_0− 

HDMI input 

Digital Input Channel 0 Complement of Port C in the HDMI Interface. 

8 

RXC_0+ 

HDMI input 

Digital Input Channel 0 True of Port C in the HDMI Interface. 

9 

CGND 

Ground 

TVDD and CVDD Ground. 

10 

RXC_1− 

HDMI input 

Digital Input Channel 1 Complement of Port C in the HDMI Interface. 

11 

RXC_1+ 

HDMI input 

Digital Input Channel 1 True of Port C in the HDMI Interface. 

12 

TVDD 

Power 

Receiver Terminator Supply Voltage (3.3 V). 

ve Serial Clock Port

e

r Comparator Supp

Compara

and CVDD Ground

CVDD Grou

al Input Clock Com

l Input Clock Co

put Clock T

put Cloc

ato

at

Harman Kardon

Page 71 of 131

ADV7623 

ADI Confidential

Rev. Sp0 | Page 10 of 16 

13 

RXC_2− 

HDMI input 

Digital Input Channel 2 Complement of Port C in the HDMI Interface. 

14 

RXC_2+ 

HDMI input 

Digital Input Channel 2 True of Port C in the HDMI Interface. 

15 

HP_CTRLD 

Digital output 

Hot Plug Detect for Port D. 

16 

5V_DETD 

Digital input 

5 V Detect Pin for Port D in the HDMI Interface. 

17 DGND  Ground 

DVDD 

Ground. 

18 

DVDD 

Power 

Digital Supply Voltage (1.8 V). 

19 

DDCD_SDA 

Digital I/O 

HDCP Slave Serial Data Port D. DDCD_SDA is a 3.3 V input/output that is 5 V tolerant. 

20 

DDCD_SCL 

Digital input 

HDCP Slave Serial Clock Port D. DDCD_SCL is a 3.3 V input that is 5 V tolerant. 

21 

CVDD 

Power 

Receiver Comparator Supply Voltage (1.8 V). 

22 

CGND 

Ground 

TVDD and CVDD Ground. 

23 

RXD_C− 

HDMI input 

Digital Input Clock Complement of Port D in the HDMI Interface. 

24 

RXD_C+ 

HDMI input 

Digital Input Clock True of Port D in the HDMI Interface. 

25 

TVDD 

Power 

Receiver Terminator Supply Voltage (3.3 V). 

26 

RXD_0− 

HDMI input 

Digital Input Channel 0 Complement of Port D in the HDMI Interface. 

27 

RXD_0+ 

HDMI input 

Digital Input Channel 0 True of Port D in the HDMI Interface. 

28 

CGND 

Ground 

TVDD and CVDD Ground. 

29 

RXD_1− 

HDMI input 

Digital Input Channel 1 Complement of Port D in the HDMI Interface. 

30 

RXD_1+ 

HDMI input 

Digital Input Channel 1 True of Port D in the HDMI Interface. 

31 

TVDD 

Power 

Receiver Terminator Supply Voltage (3.3 V). 

32 

RXD_2− 

HDMI input 

Digital Input Channel 2 Complement of Port D in the HDMI Interface. 

33 

RXD_2+ 

HDMI input 

Digital Input Channel 2 True of Port D in the HDMI Interface. 

34 

CVDD 

Power 

Receiver Comparator Supply Voltage (1.8 V). 

35 

CGND 

Ground 

TVDD and CVDD Ground. 

36 TXPVDD Power 

1.8 V Power Supply for Digital and I/O Power Supply. This pin supplies power to the  
digital logic and I/Os. It should be filtered and as quiet as possible. 

37 

TXPLVDD 

Power 

1.8 V Power Supply. 

38 TXGND  Ground 

TXPVDD 

Ground. 

39 TXPGND 

Ground 

TXPLVDD 

Ground. 

40 EXT_SWING 

Analog 

input This pin sets the internal reference currents. Place an 887 Ω resistor (1% tolerance) between 

this pin and ground. 

41 HPD_ARC− 

Analog 

input Hot Plug Detect Signal. This pin indicates to the interface whether the receiver is connected.  

It supports 1.8 V to 5 V CMOS logic levels. 

42 

ARC+ 

Analog input 

Audio Return Channel Input (5 V Tolerant). 

43 TXDDC_SDA 

Digital 

I/O  Serial Port Data I/O to Receiver. This pin serves as the master to the DDC bus. It supports a  

5 V CMOS logic level. 

44 TXDDC_SCL 

Digital 

output 

Serial Port Data Clock to Receiver. This pin serves as the master clock for the DDC bus.  
It supports a 5 V CMOS logic level. 

45 

TXAVDD 

Power 

1.8 V Power Supply for TMDS Outputs. 

46 TXGND  Ground 

TXAVDD 

Ground. 

47 TXC− 

HDMI 

output Differential Clock Output. Differential clock output at the TMDS clock rate; supports  

TMDS logic level. 

48 TXC+ 

HDMI 

output Differential Clock Output. Differential clock output at the TMDS clock rate; supports  

TMDS logic level. 

49 TXGND  Ground 

TXAVDD 

Ground. 

50 TX0− 

HDMI 

output Differential Output Channel 0 Complement. Differential output of the red data at 10×  

the pixel clock rate; supports TMDS logic level. 

51 TX0+ 

HDMI 

output Differential Output Channel 0 True. Differential output of the red data at 10× the pixel clock 

rate; supports TMDS logic level. 

52 TXGND  Ground 

TXAVDD 

Ground. 

53 TX1− 

HDMI 

output Differential Output Channel 1 Complement. Differential output of the red data at 10×  

the pixel clock rate; supports TMDS logic level. 

54 TX1+ 

HDMI 

output Differential Output Channel 1 True. Differential output of the red data at 10× the pixel  

clock rate; supports TMDS logic level. 

55 

TXAVDD 

Power 

1.8 V Power Supply for TMDS Outputs. 

l Inp

p

eiver Termina

Term

gital Input Chann

put Chann

Digital Input Chan

tal Input Cha

Receiver Compa

ceiver Comp

TVDD and CVD

DD and CVD

1.8 V Power S

1.8 V Power 

digital logi

digital log

1.8 V Pow

1.8 V Pow

TXPVD

XPVD

TXPLV

TXPL

g input 

Thi

Thi

th

th

nalog input 

Analog input 

alog input 

Digital I/O 

igital I/O 

SCL 

Digital outp

Digital ou

DD

Power 

Power 

Groun

Groun

DM

DM

ly Volta

y

 

 

Digital and I/O P

gital and I

It should be filt

It should be 

d. 

he internal refer

he internal 

ground. 

ground. 

Detect Signal. Th

ect Signal

rts 1.8 V to 5 V C

.8 V to 5

Return Channel 

urn Chann

l Port Data I/O t

rt Dat

CMOS logic leve

MOS logic 

erial Port Data C

l Port Dat

It supports a 5 V

It supports a

1.8 V Power Su

1.8 V Powe

TXAVDD Gro

TXAVDD 

Differentia

Differe

TMDS lo

TMDS

d as q

 as

rrents. Place an 887

. Place an 88

dicates to the inter

es to the inte

ic levels. 

vels. 

V Tolerant). 

nt). 

er. This pin serves

his pin serves

a

Receiver. This pin se

r. This pin s

ogic level. 

ogic level. 

r TMDS Outputs. 

 TMDS Outputs

Output. Differentia

put. Differentia

. 

ock Output. Differe

ck

evel. 

evel. 

ound. 

nd.

al Output Channe

l Output Channe

ck rate; suppo

ck rate; suppo

t Chan

t Ch

Harman Kardon

Page 72 of 131