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1
8
15
22
30
60
3
10
17
24
49
5
12
19
26
51
62, 2
9, 16
23, 29
59, 64
4, 11
18, 25
31, 61
53
41
44

56
39
58
47
37
52
43
38
54
45
40
6
13
20
27
7
14
21
28
32

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36

55
46
48

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TV
V1
V2
V3
V4
V5
V6
Y1
Y2
Y3
Y4
YIN1
C1
C2
C3
C4
CIN1
LTV, LV1
LV2, LV3
LV4, LV5
LV6, RTV
RV1, RV2
RV3, RV4
RV5, RV6
VOUT1
VOUT3
V/YOUT2

YOUT1
YOUT3
COUT1
COUT2
COUT3
LOUT1
LOUT2
LOUT3
ROUT1
ROUT2
ROUT3
S2-1
S2-2
S2-3
S2-4
S-1
S-2
S-3
S-4
ADR

SCL
SDA
DC OUT

TRAP1
TRAP2
MUTE

BIAS

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O
O
O

O
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O

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Video signal input.
Composite video signal input

Y/C-separated signal input terminal for luminance signal input.
YIN1 to feed in the Y/C-separated signal of VOUT1 output.

Y/C-separated signal input terminal for chrominance signal input.
CIN1 to feed in the Y/C-separated signal of VOUT1 output.

Audio signal input terminal.

Video signal output terminal for composite video signal output.

Video signal output terminal for selection between composite video signal output and
luminance signal output by I2C Bus control.
Video signal output terminal for luminance signal output.

Video signal output terminal for chrominance signal output.

Audio signal output terminal.

Used to detect C signal-superimposed, S2-compatible DC level. 4:3 video signal when
below 1.3V. 4:3 letterbox signal when between 1.3V and 2.5V. 16:9 image squeeze
signal when above 2.5V. To be pulled down to GDN at 100K

Ω

 to produce 4:3 video

signal when open.
Used to switch between composite video and S signals. Detection results to be written
in status register. S signal when below 3.5V. Composite video signal when above 3.5V.
To be pulled up to 5V at 100K

Ω

 to produce composite video signal when open.

Used to select I2C Bus slave address. 90H when below 1.5V. 92H when above 2.5V.
90H also when the terminal is open.
I2C Bus signal input terminal.
I2C Bus signal input terminal.
Used to feed out S2-compatible DC level to be superimposed on COUT3 output. DC to
be superimposed by connecting to COUT3 output via a capacitor. Control to be made
by I2C Bus. S2-specified output impedance of 10 ±3K

Ω

 to be realized by adding an

external resistance of 4.7K

Ω

.

Subcarrier trap circuit to be connected.

Audio signal output mute terminal. Mute off when below 1.3V. Mute on when above
2.5V. Mute off when the terminal is open.
Internal reference bias (Vcc/2) terminal. To be connected to GND with a capacitor in
between.

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12
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21
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4, 14, 39, 45, 52,
58
51
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15
53
59
24
6, 8, 16, 18, 33,
35, 37, 41, 43, 47,
49, 54, 56, 60, 62
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9
17
19
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61
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VIDEO 1-L1
VIDEO 1-L2
VIDEO 1-L3
VIDEO 2-L1
VIDEO 2-L2
VIDEO 2-L3
VIDEO 3-L1
VIDEO 3-L2
VIDEO 3-L3
VCC

AVCC
VIDEO 2-Y
VIDEO 3-Y
TUNER-Y
VIDEO 1-Y
DGND
GND

VIDEO 2-Pb
VIDEO 2-Pr
VIDEO 3-Pb
VIDEO 3-Pr
TUNER-Pb
TUNER-Pr
VIDEO 1-Pb
VIDEO 1-Pr
VIDEO 2-SW
VIDEO 3-SW
MONO-SW
VIDEO 1-SW
ADDRESS
SDA
SCL
DVCC
L3 OUT
L2 OUT
L1 OUT
Pr OUT 3
Pb OUT 3
Y OUT 3
Pr OUT 2
Pb OUT 2
Y OUT 2
Pr OUT 1
Pb OUT 1
Y OUT 1

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—

—

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—
—

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I/O

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—

O
O
O
O
O
O
O
O
O
O
O
O

Line input of D-terminal

Analog power supply (9V)

Y-signal input

GND

Pb, Pr signal input

Switch line of D-terminal

Slave address select pin
Data input of I2C bus
Clock input of I2C bus
Digital power supply (5V)
Line output for monitor

Video signal output

Ë

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99, 1, 3, 4, 2, 100,
98, 96
97, 94, 93, 89, 86,
84, 82, 79, 81, 83,
90, 85, 77, 78, 76,
71, 69
70, 68, 67

9, 10, 11, 12, 13,
14, 15, 16
41, 42, 43, 44, 45,
46, 47, 62

24, 25, 26, 27

»

D0-D7

A0-A16

A17-A19/
P4.0, P4.1, P4.4

P0.0-P0.7

P1.0-P1.7
(PWM)

P2.0-P2.3
(ADC)

I/O

O

I/O

I/O

I/O

I

Data bus for external memory or data RAM.

Address bus for external program memory or data RAM.

After power-on P4.0,P4.1,P4.4 work as additional address lines A17…A19.
In port mode, these port lines act as bi-directional I/O port with internal pull-up
resistors. Port pins that have ‘1’ written to them are pulled high by the internal pull-up
resistors and in that state can be used as inputs.
Port 0 is a 8-bit open drain bi-directional I/O-port. Port 0 pins that have 1 written to
them float: in this state they can be used as high impedance inputs.
Port is a 8-bit bi-directional multifunction I/O port with internal pull-up resistors. Port 1
pins that have 1 written to them are pulled high by the internal pull-up resistors and in
that state can be used as inputs.
The secondary functions of port 1 pins are:
Port bits P1.0-P1.5 contain the 6 output channels of the 8-bit pulse width modulation
unit.
Port bits P1.6-P1.7 contain the two output channels of the 14-bit pulse width
modulation unit.
Port 2 is a 4-bit input port without pull-up resistors.
Port 2 also works as analog input for the 4-channel-ADC.