Sony SLV-999HF / SLV-M11HF / SLV-M91HF Service Manual ▷ View online
5-1
SLV-999HF/M11HF/M91HF
SECTION 5
INTERFACE, IC PIN FUNCTION DESCRIPTION
5-1.
SYSTEM CONTR
OL —
VIDEO BLOCK INTERF
A
CE (MA-360 BO
ARD IC161)
*1
Sync
hr
oniz
ed with dr
um r
otation. 30Hz 50% duty c
ycle.
*2
Normally “L“. “H“ when CTL signal is not generated.
*3
V period “H“ pulse.
*4
Selected by REC mode. “H“ in LP mode.“
*5
Composite sync signal (positi
v
e).
Signal
RF SWP
QVD
V SYNC
HA SWP
Pin No.
1
4
*™
(™
I/O
O
O
I
O
ST
OP
FF/REW
*1
L
*4
*1
T
APE
THREADING
*1
L
*5
*1
T
APE
UNTHREADING
*1
L
*5
*1
PB
*1
*2
*5
*1
PB P
A
USE
*1
*3
*5
*1
SLO
W
*1
*3
*5
*1
CUE
*1
*3
*5
*1
x 2
*1
*2
*5
*1
REVIEW
*1
*3
*5
*1
REC
*1
L
*5
*1
REC P
A
USE
*1
L
*5
*1
5-2.
SYSTEM CONTR
OL — SER
V
O
PERIPHERAL CIRCUIT INTERF
A
CE (MA-360 BO
ARD IC161)
*1.
30Hz pulse.
*2.
Pulse at tape running.
*3.
Re
v
er
se lo
gic pulse of STEP PLS
.
*4.
“L” when drum rotation stops.
*5.
Unstable period pulse.
*6.
Pulse in period in proportional to tape speed.
*7.
360Hz pulse.
*8.
Pulse at tape running.
*9.
Approx. 2 msec period “H” or “L” pulse.
*10.
Approx. 1.5 msec period “H” or “L” pulse.
*11.
“L
” w
hen FWD SLO
W
,
“H” w
hen R
VS SLO
W
.
Signal
CAP ST
OP
STEP PLS
DRM PG
DRM FG
CAP FG
CAP D
A
DRM D
A
Pin No.
#£
(ª
$∞
$§
$¶
&•
&ª
I/O
O (O.D)
O
I
I
I
O
O
ST
OP
L
L
*4
*4
H/L
*8
*10
FF
Hi-Z (O.D)
L
*1
*7
*6
*8
*10
REW
Hi-Z (O.D)
L
*1
*7
*6
*8
*10
T
APE
THREADING
Hi-Z (O.D)
L
*5
*5
*5
*8
*10
T
APE
UNTHREADING
Hi-Z (O.D)
L
*5
*5
*5
*8
*10
PB
Hi-Z (O.D)
L
*1
*7
*6
*9
*10
PB P
A
USE
L
L
*1
*7
H/L
*8
*10
SLO
W
*3
*2
*1
*7
*2
*8
*10
CUE
Hi-Z (O.D)
L
*1
*7
*6
*9
*10
x 2
Hi-Z (O.D)
L
*1
*7
*6
*8
*10
REVIEW
Hi-Z (O.D)
L
*1
*7
*6
*9
*10
REC
Hi-Z (O.D)
L
*1
*7
*6
*9
*10
REC P
A
USE
Hi-Z (O.D)
L
*1
*7
H/L
*8
*10
5-2
5-4.
SYSTEM CONTR
OL — SYSTEM CONTR
OL PERIPHERAL CIRCUIT INTERF
A
CE (MA-360 BO
ARD IC161)
Signal
ASURA
RESET
ASURA
CS
S IN 0
S OUT 0
S CLK
Pin No.
$º
@§
@£
@¢
@∞
I/O
I
I
I
O
I
I/O Le
vel
Normally “H”, “L” when service interruption is detected or restored.
Chip select signal fr
om timer micr
opr
ocessor
.
V per
iod
“L
”
pulse
.
Serial comm
unica
tion da
ta from timer micropr
ocessor
.
V per
iod
“ L
”
pulse.
Serial comm
unica
tion da
ta to timer micr
opr
ocessor
.
V per
iod
“L” pulse.
Serial comm
unica
tion c
lock from timer micropr
ocessor
.
V per
iod
“L” pulse.
5-5.
SYSTEM CONTR
OL — A
UDIO BLOCK INTERF
A
CE (MA-360 BO
ARD IC161)
*1.
30 Hz 50 % duty pulse a
pprox. 5 msec dela
yed fr
om RF SW P
.
*1.
Uncer
tainl
y.
*2.
“L” when erasing protection tab is bent. “H” when not bent.
*3.
P
ause of period in pr
oportion to reel r
ota
ting speed.
*4.
Approx. 2 msec period “H” pulse.
*5.
Pulse at tape running.
*6.
Normally “L”. 2 msec period “H” pulse when tape top or tape end is detected.
Signal
CAM2
MODE 1 (*8)
MODE 2 (*8)
MODE 3 (*8)
MODE 4 (*8)
(IN REC PRF)
T REEL FG
S REEL FG
T/E LED
CAP ST
OP
CAP R
V
S
T SENS
S SENS
Pin No.
9
@¡
@º
!ª
!•
!∞
&¶
&§
#™
#£
#º
^¡
^™
I/O
HI-Z
I
I
I
I
I
I
I
O (O.D)
O (O.D)
O
I
I
EJECTED
L
H
H
L
L
H
H/L
H/L
*4
L
H
*4
*4
CASSETTE
LO
ADING
H
L
L
L
H
*2
H/L
H/L
*4
L
*4
*4
CASSETTE
UNLO
ADING
L
L
L
L
H
*2
H/L
H/L
*4
L
*4
*4
T
APE
THREADING
H
*1
*1
*1
*1
*2
H/L
*3
*4
H
L
*6
*6
T
APE
UNTHREADING
L
*1
*1
*1
*1
*2
H/L
*3
*4
H
H
*6
*6
ST
OP
*7
H
H
H
L
*2
H/L
H/L
*4
L
H/L
*6
*6
FF
*7
H
H
L
H
*2
*3
*3
*4
H
L
*6
*6
REW
*7
H
H
L
H
*2
*3
*3
*4
H
H
*6
*6
PB
*7
H
L
L
H
*2
*3
*3
*4
H
L
*6
*6
PB P
A
USE
*7
H
L
L
L
*2
H/L
H/L
*4
L
L
*6
*6
SLO
W
*7
H
L
L
L
*2
*3
*3
*4
*5
L/*5
*6
*6
x 2
*7
H
L
L
L
*2
*3
*3
*4
H
L
*6
*6
CUE
*7
H
L
L
L
*2
*3
*3
*4
H
L
*6
*6
REVIEW
*7
L
L
H
L
*2
*3
*3
*4
H
H
*6
*6
REC
*7
H
L
L
L
*2
*3
*3
*4
H
L
*6
*6
REC
P
A
USE
*7
H
L
L
L
*2
H/L
H/L
*4
L
L
*6
*6
*7.
When tr
ansition to UNLO
ADING dir
ection :
“L
”.
When tr
ansition to LO
ADING direction :
“H”.
When CAM MO
T
OR is stopped :
Hi-Z.
*8.
When R
VS slo
w : Mode 1=”L”
When R
VS slo
w : Mode 2=”L”
When R
VS slo
w : Mode 3=”H”
When R
VS slo
w : Mode 4=”L”
Signal
AF
ENV
A
MUTE
AF REC P
AF
SWP
FULL ERS
Pin No.
%ª
#¡
2
`⁄‚‚
#¢
I/O
I
O (O.D)
O
O
O (O.D)
ST
OP/FF/
REW
L
L
*1
H
T
APE
LO
ADING
L
L
*1
H
T
APE
UNLO
ADING
L
L
*1
H
PB
*1
L
*1
H
PB P
A
USE
H
L
*1
H
SLO
W
H
L
*1
H
x 2
H
L
*1
H
CUE
H
L
*1
H
REVIEW
H
L
*1
H
REC
L
H
*1
L
REC P
A
USE
L
L
*1
H
AF RF en
v
elope signal input ter
minal for automa
tic trac
king
.
5-3.
SYSTEM CONTR
OL — MECHANISM INTERF
A
CE (MA-360 BO
ARD IC161)
5-3
5-6. SERVO/SYSTEM CONTROL MICROPROCESSOR PIN FUNCTIONS
(MA-360 BOARD IC161)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Pin Name
RF SWP
AF REC P
AF REC
QVD
AUTO PRESET
FE ON
N.C
L.LINK
CAM 2
N.C
TA MUTE
N.C
N.C
N.C
CIN (REC PRF)
AV CONT
N.C
MODE 4
MODE 3
MODE 2
MODE 1
ENV SW
S IN 0
S OUT 0
S CLK
ASURA CS
SERVO
CAP TRQ PWM
N.C
CAP RVS
A MUTE
T/E LED
CAP STOP
FULL ERS
N.C
I2C DATA
N.C
I2C CLOCK
MP
ASURA RESET
GND
XTAL
EXTAL
N.C
DRUM PG
DRUM FG
CAP FG
NICOL ON
CBC POWER
F MONO
I/O
O
O
O
O
O
O
O
I
O
I
I
I
I
I
I
I
O
I
I
O
O
O
O
O
O
O
I/O
I/O
—
I
—
O
I
—
I
I
I
O
O
O
Function
RF switching pulse output.
“H” when HiFi audio REC.
“H” output when HiFi audio
recording.
Quasi VD pulse output.
“H” during auto preset.
Flying erase ON/OFF.
Not used.
Laser Link control out.
Cam motor control.
Not used.
Tuner audio mute. H: Mute
Not used.
Not used.
Not used.
Erasing protection tab, cassette in
detection signal input.
Not used.
Not used.
Cam encoder signal input.
Cam encoder signal input.
Cam encoder signal input.
Cam encoder signal input.
Video envelope mode detect signal
(SP or EP)
Serial communication signal.
Serial communication signal.
Serial communication signal.
Servo/system control microcomputer
chip select signal.
Not used.
PWM output for capstan torque
control.
Not used.
Capstan reverse control “L” when
reverse.
“H” when audio mute.
Tape top /end sensors driver.
Capstan stop signal output.
Full erase control.
Not used.
Serial communication data.
Not used.
Serial communication clock.
Ground.
System reset signal.
Ground.
System clock (16 MHz).
System clock (16 MHz).
Ground.
Drum PG input.
Drum FG input.
Capstan FG input.
NICOL control signal out.
Cable box control signal out.
Forced mono.
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pin Name
SW2
GND
VDD
VDD
N.C
AV ADJ
N.C
N.C
AF ENV
RF ENV
T SENS
S SENS
VDD
AMP VSS
CTL HEAD (Y)
CTL HEAD (X)
HEADL (+)
HEADL (–)
CTL FAMPI (+)
CTL FAMPI (–)
CTL AGND
CTL SAMPI
CTL FAMPO
AMP VDD
ANOUT
S REEL FG
T REEL FG
CAP DA
DRM DA
N.C
N.C
VSYNC
N.C
18 V_CONT
24 V_CONT
TEX
TX
VSS
VDD
VDD
FAST SEARCH
HA SWP
C ROT
POWER SAVE CONT
POWER SAVE C+
MOD CONT
SP
TV/VTR
STEP PLS
AF SWP
I/O
O
—
I
I
—
I
—
—
I
I
I
I
I
—
I/O
I/O
O
O
I
I
O
I
O
I
O
I
I
O
O
—
I
O
O
—
I
I
O
O
O
O
O
O
O
O
O
O
Function
Not used.
Ground.
UNSW 5 V.
UNSW 5 V.
Ground.
Adjustment mode.
Ground.
Ground.
HiFi audio playback signal envelope.
Video playback signal envelope.
Take-up end sensor.
Supply end sensor.
UNSW 5 V.
Ground.
CTL signal I/O.
CTL signal I/O.
CTL signal.
CTL signal.
CTL first AMP input.
CTL first AMP input.
Ground.
CTL second AMP input.
CTL first AMP output.
5 V.
Control signal output for check pin.
Supply reel FG input.
Take-up reel FG input.
Capstan error D/A output.
Drum error D/A output.
UNSW 5 V.
Ground.
Composite sync signal input.
Not used.
18 V control, when the high speed
mode.
24 V control, when the high speed
mode.
Not used.
Not used.
Ground.
UNSW 5 V.
UNSW 5 V.
CTL level control signal “L” when
high speed mode.
Video head switching pulse signal
output.
Color rotate pulse signal output.
Not used.
Not used.
Not used.
Tape speed mode control signal “L”
when SP mode.
TV/VTR control signal output.
Step pulse “H” when capstan step
driving.
AF switching pulse output.
5-4E
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Pin Name
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
N.C
N.C
GRID10
GRID9
GRID8
GRID7
GRID6
GRID5
GRID4
GRID3
GRID2
GRID1
VDD
TX
TEX
NC/VCC
ASURA CS
SYS RESET
POWER CONT M12
POWER CONT SW12
CG V
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
O
O
O
O
O
I
Function
Segment terminal 8.
Segment terminal 9.
Segment terminal 10.
Segment terminal 11.
Segment terminal 12.
Segment terminal 13.
Segment terminal 14.
Segment terminal 15.
Segment terminal 16.
Not used.
Not used.
Grid terminal 10.
Grid terminal 9.
Grid terminal 8.
Grid terminal 7.
Grid terminal 6.
Grid terminal 5.
Grid terminal 4.
Grid terminal 3.
Grid terminal 2.
Grid terminal 1.
D5 V
Timer clock terminal (32.768 kHz).
Timer clock terminal (32.768 kHz).
D5 V
S/S microcomputer chip select
signal.
System reset output.
Power supply control signal.
Power supply control signal.
Composite sync input.
5-7. TUNER/TIMER CONTROL MICROPROCESSOR PIN FUNCTIONS
(MA-360 BOARD IC460)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Pin Name
SYNC ON
POWER FAIL
H DET
SIRCS IN
STEREO DET
SW1 SIRCS OUT
BUZZER
N.C
ARC_LED
SCK 0
SI 0
SO 0
EEP WP
LANC IN
LANC OUT
A/D 0
A/D 1
A/D 2
A/D 3
A/D 4
ML LED
X CS
AFT
AVDD
AV REF
SCL 0
CG CS
SDA 0
JOG LED
AVSS
EXTAL
XTAL
VSS
RST
PLL CLK
PLL DATA
PLL ENABLE
MAIN/SAP
SAP DET
V SET CS
DMS 1
DMS 2
VFDP
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
I/O
O
I
I
I
I
O
O
O
I
I
O
O
I
O
I
I
I
I
I
O
O
I
I
O
O
O
O
I
I
I
O
O
O
O
I
O
I
I
I
O
O
O
O
O
O
O
Function
During Laser Link signal resived “H”.
Power failure detect signal input.
H DET_(Tuner Hsync detect input).
Remote control signal input.
Stereo judge input.
Remote control signal output.
Buzzer signal output.
Not used.
ARC led control “H” when ARC on.
Serial communication signal (clock).
Serial communication signal
(data in).
Serial communication signal
(data out).
EEP mode control.
LANC input.
LANC output.
Analog voltage (key) input.
Analog voltage (key) input.
Analog voltage (key) Input.
Analog voltage (key) Input.
Analog voltage (key) Input.
ML LED ON/OFF control.
Memory label board chip select
signal out.
Auto fine tuning signal input.
A/D port reference input.
UNSW 5 V.
T BUS (clock) /IIC BUS (clock).
Character generator chip select
signal.
IIC BUS (data).
JOG LED control signal output.
Ground.
System clock terminal (16 MHz).
System clock terminal (16 MHz).
Ground.
RESET input.
TUNER PLL clock.
TUNER PLL data.
TUNER chip select.
Main/SAP judge signal output.
Main/SAP judge signal input.
Vset IC chip select signal.
DMS forward/reverse signal input.
DMS forward/reverse signal input.
VFDP.
Segment terminal 1
Segment terminal 2
Segment terminal 3
Segment terminal 4
Segment terminal 5
Segment terminal 6
Segment terminal 7
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