Sony SLV-7700KML Service Manual ▷ View online
6-9
Pin No.
Pin Name
I/O
Function
40
A17
O
41
A18
O
A
d
d
ress b
us output.
42
A19
O
43
MPEG
I
MPEG w
ait input.
44
MD0
I
Operation mode setting terminal. (Connected to +5V)
45
MD1
I
Operation mode setting terminal. (Connected to ground)
46
Ø
O
System clock output (Not used).
47
STBY
I
Shifts to the hard
w
ar
e standby mode when the standby terminal becomes
“Lo
w”. (Unable to use H le
v
el f
ix
ed) (Connected to +5V)
48
RESET
I
Set into reset w
hen the r
eset input pin becomes
“Lo
w”.
49
NM1
I
Requests mask disable inter
ruption. (Unable to use H le
v
el f
ix
ed)
(Connected to +5V)
50
VSS
–
GND.
51
EXT
AL
I
Connected to the Cr
ystal oscilla
tor
.
T
he EXT
AL pin is also a
b
le to
input e
xter
nal cloc
ks.
52
XT
AL
I
Connected to the Crystal oscillator
.
53
VCC
–
Connect to the po
wer supply
. (+5V)
54
AS
O
When the addr
ess strobe pin is
“Lo
w”,
indicates that addr
ess outputs on
the addr
ess b
us ar
e v
alid
.
55
RD
O
When the read pin is
“Lo
w”,
indicates tha
t the e
xter
nal addr
esses space is
in the read state.
56
WR
O
When the read pin is
“Lo
w”,
indicates tha
t the e
xter
nal addr
esses space is
in the wr
ite sta
te and the da
ta b
us are v
alid
.
57
RESO
O
Reset output (Not used).
58
A
VSS
–
A/D con
v
er
ter (pin62-69) gr
ound
.
59
TEST0
I
T
est 0 input.
60
TEST1
I
T
est 1 input.
61
TEST2
I
T
est 2 input.
62
SENS
I
Internal state (SENSE) monitor input from BD-21 board.
63
D
A
C-SELECT
I
A
udio D/A con
v
er
ter select mode setting ter
minal.
64
NPIN
I
NTSC/P
AL output mode setting ter
minal.
65
CXD1853-SELECT
I
CXD1853 select mode setting terminal. (H : CXD1853 used)
66
VREQ
I
Not used.
67
VREF
I
A/D con
ver
ter (pin62-69) r
ef
er
ence v
olta
ge input. (connected to +5V)
68
A
VCC
–
A/D con
ver
ter (pin62-29) po
wer supply
. (connected to +5V)
69
CXD1913L
TH
O
Serial data latch pulse output to CXD1913. (Digital NTSC/P
AL encoder)
70
XHIRQ
I
Interr
uption request input from MPEG decoder
.
71
SCOR
I
Subcode sync input from BD-21 board.
72
MREQ
I
Inputs command r
equest fr
om system contr
oller
.
Pin No.
Pin Name
I/O
Function
73
D
A
T
A
O
Serial data output to BD-21 board, CXD1913 and CXD8567.
74
AMUTE
O
Mute switching to BD-21 board.
75
LDON
O
Laser diode ON/OFF output.
76
XL
T
O
Latch output to BD-21 board.
77
SCLK
O
SENS serial data reading clock output to BD-21 board.
78
CLK
O
Serial data clock output to BD-21 board and CXD1913.
79
NP OUT
O
NTSC/P
AL output select.
80
2545RST
O
Dig
ital signal pr
ocessor
. (CXD2545Q system r
eset)
6-10
Pin No.
Pin Name
I/O
Function
CAS signal. Connect to the CAS pin of the DRAM so as to control the
36
XCAS2
O
lo
w
er b
ytes of the upper wor
d
(256K to 512K-1) f
or the 256Kw
×
16b
/MA9
×
2 DRAM structure. /Address signal pin. Connect to the DRAM address
pin with the same number
.
CAS signal. Connect to the CAS pin of the DRAM so as to control the
37
XCAS0
O
lo
w
er b
ytes (MD0 to MD7) f
or 256Kw
×
16b and 512Kw
×
8b
×
2 DRAM str
uctures,
and to contr
ol the lo
wer b
ytes of the lo
wer wor
d
(0 to 256K-1) for the 256Kw
×
16b
×
2 DRAM structure.
38
MD7
I/O
39
MD8
I/O
40
MD6
I/O
Data input/output signal pin. Connect to the DRAM data pin so that the
4
1
M
D
9
I/
O
lo
w
er and upper bytes of the da
ta correspond to the CAS0 to CAS3 controls.
42
MD5
I/O
43
MD10
I/O
44
VDD
–
+5V po
wer suppl
y.
45
VSS
–
GND.
46
MD4
I/O
47
MD11
I/O
48
MD3
I/O
49
MD12
I/O
50
MD2
I/O
Data input/output signal pin. Connect to the DRAM data pin so that the
51
MD13
I/O
lo
w
er
and upper bytes of the da
ta correspond to the CAS0 to CAS3 controls.
52
MD1
I/O
53
MD14
I/O
54
MD0
I/O
55
MD15
I/O
56
XOSDEN
I
OSD enable signal.
57
OSDB
I
OSD da
ta input pin.
When the XOSDEN input is L, the color r
egister
ed
58
OSDG
I
in the r
egister specif
ied by this 3 inputs (3 bits) is output as the ima
g
e
59
OSDR
I
data. (Connected to ground)
60
VDD
–
+5V po
wer suppl
y.
61
VSS
–
GND.
V
ideo output enable signal pin.
When set to
‘L
’, ena
bles the image da
ta
62
XV
OE
I
output and DCLK output.
When set to ‘H’,
disa
bles (high impedance).
Output contr
ol can also be perf
or
med by writing in the re
g
ister
.
63
R/Cr0
O
64
R/Cr1
O
Output pin of the R or Cr signal of the image data. MSB is R/Cr7.
65
R/Cr2
O
Synchronizes with DCLK.
66
R/Cr3
O
6-1
1. MPEG DECODER PORT FUNCTION DESCRIPTION (CD-169 BOARD IC305 CXD1852Q)
Pin No.
Pin Name
I/O
Function
1
VSS
–
GND.
2
XTL0O
O
V
ideo decoder master cloc
k pin. Input the XTL0I c
loc
k or connect an
oscillator between XTL0I and XTL0O
.
T
he recommended fr
equencies
3
XTL0I
I
ar
e 27 MHz, 28.6363 MHz (NTSC 8fsc),
and 35.4686 MHz (P
AL 8fsc).
4
VDD
–
+5V po
wer suppl
y.
5
HA2
I
A
ddr
ess input pin. In some cases,
ser
v
es as the control signal and data
6
HA3
I
input according to the setting of the control mode.
7
HD0
I/O
8
HD1
I/O
9
HD2
I/O
10
HD3
I/O
Data input/output.
11
HD4
I/O
12
HD5
I/O
13
HD6
I/O
14
VDD
–
+5V po
wer suppl
y.
15
VSS
–
GND.
16
HD7
I/O
Data input/output.
17
MA3
O
18
MA4
O
1
9
M
A
2
O
A
ddress signal pin. Connect to the DRAM ad
dr
ess pin with the same n
umber
.
20
MA5
O
21
MA1
O
22
VSS
–
GND.
2
3
M
A
6
O
A
ddress signal pin. Connect to the DRAM ad
dr
ess pin with the same n
umber
.
24
MA0
O
25
BC
I
26
TCKI
I
27
TDI
I
F
or test.
28
TEN
AI
I
29
TDO
I
30
VST
I
F
or test. (Connect to gr
ound)
31
VSS
–
GND.
32
MA7
O
Address signal pin. Connect to the DRAM address pin with the same
33
MA8
O
n
umber
.
34
XRAS
O
RAS signal pin. Connect to the RAS pin of the DRAM. Same for the
256Kw
×
16b, 256Kw
×
16b
×
2, and 512Kw
×
8b
×
2 DRAM structures.
35
XMWE
O
WE signal pin. Connect to the
WE pin of the DRAM.
6-11
Pin No.
Pin Name
I/O
Function
Composite b
lanking signal pin. Ser
ves as an output w
hen the b
uilt-in
95
CBLNK
I/O
sync generator is used, and as an input when not. /Signal obtained by
/FSC
/O
frequency-di
viding the c
lock input from XTL0I or XTLI.
When the input
clock is 8 fsc, it can be used as the fsc signal. (Not used. open)
96
CSYNC
O
Composite sync signal pin.
A signal is made by fr
equenc
y-di
viding the
DCLK. Cannot be input.
97
XSGRST
I
Sync genera
tor r
eset signal pin. The signal g
enerator is initialized b
y
setting
this pin to ‘L
’.
98
CLK0O
O
Outputs the frequency-di
vided clock of the clock input to XTL0I.
T
he fr
e
quency di
viding r
atio can be selected from 1/2, 1/4, and 1/8.
99
DOUT
O
Digital output. (Not used. open)
1
0
0
D
A
TO
O
Audio serial data output pin. Synchronizes with the clock input from FSXI.
101
LRCO
O
LR clock output pin. Outputs the clock input from the LRCI.
(Not used. open)
102
BCK
O
O
Bit clock output pin. Outputs the clock input from the BCKI.
(Not used. open)
103
FSXI
I
Input 384fs (16.9344 MHz) or 768fs (33.8688 MHz).
104
VDD
–
+5V po
wer suppl
y.
105
VSS
–
GND.
106
XTL2O
O
CD-R
OM decoder
, audio decoder master c
loc
k. Input a c
loc
k to the XTL2I
or connect an oscillator between XTL2I and XTL2O
.
T
he recommended
107
XTL2I
I
frequency is 45 MHz.
T
his c
lock is for the internal cir
cuit. Does not
synchronise with inputs and outputs.
108
VDD
–
+5V po
wer suppl
y.
109
C2PO
I
C2 pointer input.
110
LRCI
I
LR clock input.
111
D
A
TI
I
Serial data input.
112
BCKI
I
Bit clock input.
113
DOIN
I
Digital input signal.
114
XHCS
I
R
eg
ister access c
hip select signal pin.
115
XHDT
I/O
Data ac
kno
wledg
e/wait signal pin f
or DMA tr
ansmission, r
eg
ister access,
transparent memory access.
116
HR
W
I
Re
gister access contr
ol signal pin.
117
XHIRQ
O
Interrupt request signal.
118
XRST
I
Har
dwar
e reset input pin.
When set to
‘L
’, all re
gister
s and opera
tions ar
e
reset and initialized.
1
1
9
H
A
0
I
A
ddr
ess input pin. In some cases, serv
es as the contr
ol signal and da
ta
120
HA1
I
input according to the setting of the control mode.
Pin No.
Pin Name
I/O
Function
67
R/Cr4
O
68
R/Cr5
O
Output pin of the R or Cr signal of the image data. MSB is R/Cr7.
69
R/Cr6
O
Synchronizes with DCLK.
70
R/Cr7
O
71
G/Y0
O
72
G/Y1
O
Output pin of the G or
Y signal of the image da
ta. MSB is G/Y7.
73
G/Y2
O
Synchronizes with DCLK.
74
VDD
–
+5V po
wer suppl
y.
75
VSS
–
GND.
76
G/Y3
O
77
G/Y4
O
78
G/Y5
O
Output pin of the G or
Y signal of the image da
ta. MSB is G/Y7.
79
G/Y6
O
Synchronizes with DCLK.
80
G/Y7
O
81
B/Cb0
O
82
B/Cb1
O
83
B/Cb2
O
84
B/Cb3
O
Output pin of the B or Cb signal of the image data. MSB is B/Cb7.
85
B/Cb4
O
Synchronizes with DCLK.
86
B/Cb5
O
87
B/Cb6
O
88
B/Cb7
O
Dot clock (DCLK) signal pin.
T
he DCLK frequenc
y is normally
89
DCLK
I/O
13.5 MHz.
The DCLK can be input from this pin or can be made b
y
fr
equenc
y-
di
viding (1/integer) the clock input from XTL0I.
90
VDD
–
+5V po
wer suppl
y.
91
VSS
–
GND.
Horizontal sync signal pin.
When using the b
uilt-in sync gener
ator
,
92
HSYNC
I/O
a signal is made by fr
equency-di
viding the dot c
loc
k (DCLK). Ser
ves as
the input w
hen not using the b
uilt-in sync gener
ator
.
V
er
tical sync signal pin.
When using the b
uilt-in sync gener
ator
, a signal
93
VSYNC
I/O
is made b
y
fr
equenc
y-di
viding the DCLK. Ser
v
es as the input when not
using the b
uilt-in sync gener
ator
.
F
ield determina
tion signal signal. Od
d f
ield cor
respond to H and e
v
en
FID
I/O
field correspond to L. Serv
es as an output when the b
uilt-in sync generator
94
/FHREF
/O
is used
, and as an input when not. /Signal obtained by fr
equenc
y-di
viding
the c
loc
k input from XTL0I or XTLI.
When the input clock is 8 fsc,
it can
be used as the horizontal sync signal phase comparison reference signal.
6-12
Pin No.
Pin Name
I/O
Function
10-bit D/A con
v
er
ter output. (Not used
. open)
32
CO
O
When control r
egister bit “YC/YUV”=“1”, outputs the c
h
roma (C) signal.
When contr
ol r
egister bit
“YC/YUV”=“0”,
outputs the color dif
fe
rence
(U) signal.
T
est da
ta b
us.
33
TD10
I/O
Set to open.
In the test mode,
used f
or internal cir
cuit test da
ta b
us.
T
he test mode is allo
wed to use onl
y f
or device v
endor
s.
34
VDD
–
Dig
ital po
wer supply
.
35
TD9
I/O
T
est da
ta b
us.
Set to open.
36
TD8
I/O
In the test mode,
used f
or internal cir
cuit test da
ta b
us.
T
he test mode is allo
wed to use onl
y f
or device v
endor
s.
37
XTEST1
I
T
est mode contr
ol input pin. Pulled-up.
38
XTEST2
I
When these pins are “H”, CXD1913Q is not in the test mode.
39
XTEST3
I
T
he test mode is allo
wed to use onl
y f
or device v
endor
s.
40
VSS
–
Digital GND.
41
TRST
I
T
est mode reset input pin.
During po
wer on/reset, set to “L
” f
or more than 40 c
locks (SYSCLK).
42
VDD
–
Dig
ital po
wer supply
.
43
TDI
I
T
est mode contr
ol input pin. Pulled-up.
44
TMS
I
45
TCK
I
T
est mode contr
ol input pin. Fix at “H”.
46
TDO
O
T
est da
ta b
us pin. Set to open.
47
VSS
–
Digital GND.
The functions of this pin are selected by pin 64 XIICEN.
When the XIICEN pin is “H”, sets into the SONY SIO mode, and becomes
48
SI
I
the SI serial data input pin.
When the XIICEN pin is “L”, sets into the I
2
C-B
US mode
, and becomes the
SD
A input/output pin.
The functions of this pin are selected by pin 64 XIICEN.
When the XIICEN pin is “H”, sets into the SONY SIO mode, and becomes
49
SCK
I
the SCK serial clock input pin.
When the XIICEN pin is “L”, sets into the I
2
C-B
US mode
, and becomes the
SCL input pin.
The functions of this pin are selected by pin 64 XIICEN. Pulled-up.
When the XIICEN pin is “H”, sets into the SONY SIO mode, and becomes
50
XCS
I
the XCK chip select input pin.
When the XIICEN pin is “L”, sets into the I
2
C-B
US mode
, and becomes the
SA sla
ve
ad
dress selection input signal w
hich selects the I
2
C-B
US sla
ve
ad
dress.
6-12. VIDEO ENCODER PORT FUNCTION DESCRIPTION (CD-169 BOARD IC310 CXD1913Q)
Pin No.
Pin Name
I/O
Function
1
Y
7
I
8-bit pix
el da
ta input pins (PD0 to 7).
2
Y
6
I
When control r
egister bit “PIF MODE”=“0”, ser
ve as input pins f
o
r
3
Y
5
I
m
ultiple
x
ed
Y
, Cb
, Cr signals.
4
Y
4
I
When control re
gister bit
“PIF MODE”=“1”,
serve as input pins f
or
Y signal.
5
VSS
–
Digital GND.
6
Y
3
I
8-bit pix
el da
ta input pins (PD0 to 7).
7
Y
2
I
When control r
egister bit “PIF MODE”=“0”, ser
ve as input pins f
o
r
8
Y
1
I
m
ultiple
x
ed
Y
, Cb
, Cr signals.
9
Y
0
I
When control re
gister bit
“PIF MODE”=“1”,
serve as input pins f
or
Y signal.
10
VDD
–
Dig
ital po
wer supply
.
11
C7
I/O
8-bit pix
el da
ta input pins/test da
ta b
us.
1
2
C
6
I/
O
When control re
gister bit
“PIF MODE”=“0”,
these input pins cannot be used
.
13
C5
I/O
When control r
egister bit “PIF MODE”=“1”, ser
ve as input pins f
o
r
14
C4
I/O
m
ultiple
x
ed Cb,
Cr signals.
15
C3
I/O
16
C2
I/O
In the test mode,
used f
or internal cir
cuit test da
ta b
us.
17
C1
I/O
T
he test mode is allo
wed to use onl
y f
or device v
endor
s.
18
C0
I/O
19
VSS
–
Digital GND.
20
IREF
O
Reference current output pin.
Connect r
esistor
×
16 times (“16R”) of the output resistance v
alue
“R”.
21
VREF
I
V
olta
g
e ref
er
ence input pin.
Sets the output full-scale v
alue.
22
A
VDD1
–
Analo
g po
wer suppl
y.
23
A
VSS1
–
Analog GND.
10-bit D/A con
v
er
ter output.
24
COMPO
O
When control r
egister bit “YC/YUV”=“1”, outputs the composite signal.
When contr
ol r
egister bit
“YC/YUV”=“0”,
outputs the color dif
fe
rence
(V) signal.
25
VB
O
Connect to
VSS with an a
ppr
o
x. 0.1 µF ca
pacitor
.
26
V
G
I
Connect to
A
VDD with an approx. 0.1 µF ca
pacitor
.
27
A
VDD2
–
Analo
g po
wer suppl
y.
28
A
VSS2
–
Analog GND.
29
Y
O
O
10-bit D/A con
v
er
ter output. (Not used
. open)
(Luminance (Y) signal output.)
30
A
VDD3
–
Analo
g po
wer suppl
y.
31
A
VSS3
–
Analog GND.
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