DOWNLOAD Sony KV-32XBR400 Service Manual ↓ Size: 9.17 MB | Pages: 119 in PDF or view online for FREE

Model
KV-32XBR400
Pages
119
Size
9.17 MB
Type
PDF
Document
Service Manual
Brand
Device
TV
File
kv-32xbr400.pdf
Date
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—
 37 
—
K
V-32XBR400/36XBR400/36XBR400H/38DRC1/38DRC1C
Register
No & Name
Comment
UBLK = 7
UBLK = 6
UBLK = 5
UBLK = 4
UBLK = 3
UBLK = 2
UBLK = 1
UBLK = 0
 #15 DCTR (Cont.)
3
2
2
2
1
1
1
1
 #16 DPIC (Cont.)
2
3
2
1
3
2
1
0
 #17 DSBO (Cont.)
7
7
7
7
7
7
7
7
 #18 ABLM (Cont.)
1
0
0
1
0
0
0
0
Data Initial/Average Settings
(32V&36V CRTs)
DX1A SERVICE LIST (#3-4):   
CXA2150P-4  {Picture Controls: P4}
   
(Part-3/4)
Control Register
Function & Link
Data
Type
Data
Range
Comment
19 ABLT  ABL_TH: ABL currect detection Vth control
0~15
20 ABLC  Control of CXA2026 {0Ch -- DAC0} (*)
0~255
21 EPOF  Offset for UPIC = EPOF x (UPIC/63) (for power save) --- Void 
---
0~31
 ID-1 and P&P Modes
22 SPOF  Offset for UPIC = SPOF x (UPIC/64) --- Data Not Used
---
0~31
YPbPr
480i
YPbPr
480p
YPbPr
1080i
23 SCON  SUB_CONTRAST: SUB PICTURE
0~15
8
11
10
24 CLOF  Offset for UCOL
0~(7)~1
8
9
7
25 HUO  Offset for UHUE
0~7~15
3
3
3
 CXD2085 Service Controls
26 IDSW  Switch for activating the selection in #26 DATA
C
0, 1
0
27 DATA  Selection of geometry-forced vertical compression modes
C
0~3
DX1A SERVICE LIST (#3-4):   
CXA2150P-4  {Picture Controls: P4
}   
(Part-4/4)
Full
Vcomp1
Vcomp2
Register
No & Name
Data Initial/Average Settings
(32V&36V CRTs)
0
0
66
0 (Not used)
UHF/VHF
Video1~4
P&P
9
9
8
8
4
4
Full
Vcomp1
Vcomp2
0
1
2
 Full:
 480p/960i
 (4x3)
 Vcomp1:
 480p/960i
 (16x9) 
 Vcomp2:
 1080i
 (16x9)
 ( ): Settings at
       center
 C:
 Common data
—
 38 
—
K
V-32XBR400/36XBR400/36XBR400H/38DRC1/38DRC1C
Control Register
Function & Link
Data
Type
Data
Range
Comment
Full
Vcomp1
Vcomp2
0
VPOS
 V_POSITION: Vertical position (V_DRV siganl DC-b Adj.
0~(31)~63
1
VSIZ
 V_SIZE: Vertical size (V_DRV signal gain)
Adj.
0~(31)~63
2
VLIN
 V_LINEARITY: Vertical linearity
(Gain for V DRV signal secondary component)
Adj.
0~(7)~15
3
VSCO
 S_CORRECTION: Vertical S-correction
Adj.
0~(7)~15
4
VCEN
 VSAW0_DCH/VSAW0_DCL: Vertical center 
adjustment
VSAW0 DCH: VSAW0 waveform DC component
Adj.
0~(31)~63
 VCEN-L(Low bit)
 VCEN-H(High bit)
5
VPIN
 VSAW0_AMP: Vertical PIN adjustment
VSAW0 waveform SAW component amplitude
Adj.
0~(15)~31
15  [15]
 [Copy1]: Copy the adjusted data
                for Full mode.
6
NSCO
 VSAW1_DC: Rotation
Adj.
0~(7)~15
7
HTPZ
 VSAW1_AMP: Horizontal trapezoid
Adj.
0~(15)~31
8
ZOOM
 ZOOM_SW: Zoom switch
0, 1
0
9
APSW
 ASP_SW: Aspect switch
0, 1
1
1
0
10
ASPT
 V_ASPECT: Aspect ratio
Adj.
0~63
47
47
47
11
SCRL
 V_SCROLL: Vertical scroll
Adj.
0~(31)~63
31
32
32
12
UVLN
 UP_VLIN: Upper vertical linearity
0~15
0
13
LVLN
 LO_VLIN: Lower vertical linearity
0~15
0
DX1A SERVICE LIST (#4-1):   
CXA2150D-1  {Deflection Controls: D1}
7  [7]
 Device Name:     CXA2150Q  { CRT Driver / SONY } / IC201 (A-board) / P/N: 8-752-093-35 (SBorSD#: NA)
 Slave Address:   86h
15  [Copy1]
19  [19]
0
0
 Note:
8  [8]
 Either 7 or 8 can be used as the
 average NSCO data.
 (If both of them are not good,
 please feedback to / check with
 the DY attachment process.)
 Full: 480p/960i (4x3) display
 Vcomp1: 480p/960i (16x9) display
 Vcomp2: 1080i (16x9) display
 Adj.: Adjusted data
 ( ): Settings at center
Data Initial Settings & [Average Data]
(
32V&36V CRTs)
Register
No & Name
26  [26]
0
9  [9]
31  [31]
15  [15]
—
 39 
—
K
V-32XBR400/36XBR400/36XBR400H/38DRC1/38DRC1C
Control Register
Function & Link
Data
Type
Data
Range
Comment
Full
Vcomp1
Vcomp2
0
HCNT
 HC_PARA_DC: Horizontal center
Adj.
0~(31)~63
1
HPOS
 H_POSITION: Horizontal position
Adj.
0~(31)~63
31
[Adj.-6steps]
2
HSIZ
 H_SIZE: Horizontal size
Adj.
0~(31)~63
3
SLIN
 MP_PARA_DC: Horizontal S-correction
Adj.
0~15
4
MPIN
 MP_PARA_AMP: Horizontal middle pin
0~15
5
PIN
 PIN_AMP: Horizontal pin
Adj.
0~(31)~63
6
UCP
 UP_CPIN: Upper corner pin
Adj.
0~(31)~63
7
LCP
 LO_CPIN: Lower corner pin
Adj.
0~(31)~63
8
UXCG
 UP_UCG: Upper extra corner pin gain
0~3
9
LXCG
 LO_UCG: Lower extra corner pin gain
0~3
10
UXCP
 UP_UCP: Upper extra corner pin position
0~3
11
LXCP
 LO_UCP: Lower extra corner pin postion
0~3
12
XCPP
 UC_POL: Extra corner pin polarity
0, 1
13
PPHA
 PIN_PHASE: Pin phase
Adj.
0~(31)~63
14
VANG
 AFC_ANGLE: AFC angle
Adj.
0~(31)~63
15
LANG
 HC_PARA_PHASE: Linearity angle
Adj.
0~(31)~63
16
VBOW
 AFC_BOW: AFC bow
Adj.
0~(31)~63
17
LBOW
 HC_PARA_AMP: Linearity bow
Adj.
0~(31)~63
18
CPY1
 Copy Function 1: (Set CPY1=1, then press MUTE + 
nter.)
Micro
0, 1
 For engineering design use only
DX1A SERVICE LIST (#4-2):   
CXA2150D-2  {Deflection Controls: D2}
0
31  [31]
2
45  [45]
3  [3]
Data Initial Settings & [Average Data]
(32V&36V CRTs)
Register
No & Name
 Data 
(32Vor36V)
:
 The data for 36V are used as the
 Initial & CBA data.
 From the system micro (V 2.0),
 the deflection control-related
 initial settings are the same as
 their average data.
2
0
31  [31]
 Note:
 Device Name:      CXA2150Q  { CRT Driver / SONY } / IC201 (A-board) / P/N: 8-752-093-35 (SBorSD#: NA)
 Slave Address:   86h
31
[31]
31  [31]
9
 (32V)
 
or 7
 (36V)
35  [35]
2
 (32V)
 or 1 
(36V) 
31  [31]
38  [38]
42  [42]
15  [15]
31  [31]
2
 Full: 480p/960i (4x3) display
 Vcomp1: 480p/960i (16x9) display
 Vcomp2: 1080i (16x9) display
 ( ): Settings at center
 Adj.: Adjusted data
 [Adj.-6steps]:
 The adj. data for Vcomp2 mode
 = The adj. data for Full/Vcomp1
—
 40 
—
K
V-32XBR400/36XBR400/36XBR400H/38DRC1/38DRC1C
Control Register
Function & Link
Data
Type
Data
Range
Comment
Full
Vcomp1
Vcomp2
0
HBLK
 HBLK_SW: Horizontal blanking switch
0, 1
1
LBLK
 LEFT_BLK: Left blanking
0~63
50
2
RBLK
 RIGHT_BLK: Right blanking
0~63
27
3
VBLK
 VBLK_SW: Vertical blanking switch
0,  1
1
4
TBLK
 UP_BLK: Top blanking
0~(7)~15
1
8
12
 ( ): Settings at center
5
BBLK
 LO_BLK: Bottom blanking
0~(7)~15
0
13
13
6
VCMP
 V_COMP: Vertical compensation
0~15
0
0
0
7
HCMP
 H_COMP: Horizontal compensation
0~15
0
8
ACMP
 AFC_COMP: AFC compensation
0~7
0
9
PCMP
 PIN_COMP: Pin compensation
0~7
0
10
AFCM
 AFC_MODE: AFC loop gain
0~3
2
11
VFRQ
 V_FREQ: Vertical frequency
0~3
12
VON
 V_ON: Vertical drive on
0, 1
13
JUMP
 JMP_SW: Reference pulse jump swtich
0,  1
0
14
VDJP
 VDRV_SW: Vertical drive jump switch
0,  1
0
0
1
15
VDST
 RST_SW: Vertical drive start switch
0,  1
0
0
1
16
EWDC
 EW_DC: Pin DC level shift
0,  1
0
17
AKBT
 AKBTIM: AKB timing
0~31
20
20
10
1
Data Initial/Average Settings
(32V&36V CRTs)
Register
No & Name
DX1A SERVICE LIST (#4-3):   
CXA2150D-3  {Deflection Controls: D3}
3
1
1
1
45
24
 Full: 480p/960i (4x3) display
 Vcomp1: 480p/960i (16x9) display
 Vcomp2: 1080i (16x9) display
0
1
0
0
 Note:
0
 Device Name:      CXA2150Q  { CRT Driver / SONY } / IC201 (A-board) / P/N: 8-752-093-35 (SBorSD#: NA)
 Slave Address:   86h
Control Register
Function & Link
Data
Type
Data
Range
Comment
480i
(15.75 KHz)
480p
(31.50 KHz)
1080i
(33.75 KHz)
0
MTRX
 MAT_OUT: Selection of color matrix conversion types
Micro
0~3
0
0
1
1
GAIN
 GAIN_SEL:
Selection of output signals for S LYOUT, S LCBOUT, S LCROUT
C
0~3
0
2
CBGN
 YGAIN, CBGAIN, CRGAIN:
The gain control of S LYOUT, S LCBOUT, & S LCROUT
C
0~15
9
3
VTC
 V_TC: Setting of Vsync separation time constant
C
0~3
1
4
HWID
 H_WIDTH: Setting of the output pulsewidth of SELHOUT 
C
0~3
1
Video5
Video6
Sub
5
HSEP
 HSEP_SEL: Setting for the sync separation system
0,  1
0
0
0
6
TEST
 TEST: Test mode selection (for device tests)
C
0,  1
0
7
FRGB
 The forced RGB selection (for tests)
{0: MAT OUT = MTRX (#0), 1: MAT OUT = MTRX (#3)}
C
0, 1
0
Full
Vcomp1
Vcomp2
8
HMSK
 Hsync masking in vertical retrace
0,  1
0
 Note:
1
 Video5&6:
 YPbPr-480i/480p/1080i inputs
 Sub: 480i input from the sub-channel
 Full: 480p/960i (4x3) display
 Vcomp1: 480p/960i (16x9) display
 Vcomp2: 1080i (16x9) display
 C: Common data
Register
No & Name
Data Initial/Average Settings
(
32V&36V CRTs)
 Device Name:     CXA2151Q  { Component I/F & Sync Seperation / SONY } / IC3001 (B-board) / P/N: 8-752-093-84 (SD#: S00302B)
 Slave Address:   84h
DX1A SERVICE LIST (#5):   
CXA2151Q
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