Sony KE-32TS2E / KE-32TS2U Service Manual ▷ View online
-5-
(2) LVDS Signal Definition and Function
A video signal (display data signal and control signal) is converted from parallel data to serial data with the LVDS
transmitter and further converted into four sets of differential signals before input to this product.
These signals are transmitted seven times faster than dot clock signals.
The dot clock signal is converted into one set of differential signals by the transmitter before input to this product.
The LVDS signal definition and function are summarized below:
transmitter and further converted into four sets of differential signals before input to this product.
These signals are transmitted seven times faster than dot clock signals.
The dot clock signal is converted into one set of differential signals by the transmitter before input to this product.
The LVDS signal definition and function are summarized below:
Signal name
Symbol
Number
of signals
Signal definition and function
RXIN0-
RXIN0+
1
1
1
Display data signal
R0,R1,R2,R3,R4,R5,G0
RXIN1-
RXIN1+
1
1
1
Display data signal
G1,G2,G3,G4,G5,B0,B1
RXIN2-
RXIN2+
1
1
1
Display data signal, Sync Signal, Control signal
B2,B3,B4,B5
_____ _____ _______
Hsync, Vsync, BLANK
_____ _____ _______
Hsync, Vsync, BLANK
Video signal
Timing signal
Transmission line
RXIN3-
RXIN3+
1
1
1
Display data signal, Control signal
R6,R7,G6,G7,B6,B7,PARITY
Clock transmission line
RXCLKIN-
RXCLKIN+
1
1
1
Clock signal
_____
DCLK
_____
DCLK
-6-
(3) Video Signal Definition and Function
The table below summarizes the definitions and functions of input video signals before
LVDS conversion.
LVDS conversion.
Item
Signal name
Number
of
signals
Input/
output
Signal definition and function
Video signal
(digital RGB)
(digital RGB)
DATA-R
DATA-G
DATA-B
DATA-G
DATA-B
8
8
8
8
8
Input
Display data signal
R7/G7/B7 is the highest intensity bit.
R0/G0/B0 is the lowest intensity bit.
R7/G7/B7 is the highest intensity bit.
R0/G0/B0 is the lowest intensity bit.
Data Clock
DCLK
1 Input
Display data timing signal: Data are read
when DCLK is low. DCLK is continuously
input.
when DCLK is low. DCLK is continuously
input.
Horizontal sync
signal
_____
Hsync
Hsync
1 Input
Regulates one horizontal line of data: Begins
control of the next screen when Hsync is
lowered.
control of the next screen when Hsync is
lowered.
Vertical sync
signal
_____
Vsync
Vsync
1 Input
Screen starts up control timing signal: Begins
control of the next screen when Vsync is
lowered.
Input the same frequency in both
odd-numbered and even-numbered fields.
control of the next screen when Vsync is
lowered.
Input the same frequency in both
odd-numbered and even-numbered fields.
Parity signal
PARITY
1
Input
This signal specifies the display field.
H: Odd-numbered field
L: Even-numbered field
L: Even-numbered field
Parity signal should be alternated in every
Vsync cycle. This signal is arbitrarily
reversed internally when there is no reversing
signal.
Vsync cycle. This signal is arbitrarily
reversed internally when there is no reversing
signal.
Original
Display
signal
(before
LVDS
transmitta
nce)
Display
signal
(before
LVDS
transmitta
nce)
Blanking signal
BLANK
1
Input
Display period timing signal.
H indicates the display period and L indicates
the non display period.
Note:
Set this timing properly like followings, as is
used internally for signal processing.
・
H indicates the display period and L indicates
the non display period.
Note:
Set this timing properly like followings, as is
used internally for signal processing.
・
Set the blanking period so that the number
of effective display data items in one
horizontal period is 852.
・
horizontal period is 852.
・
Set the number of blanking signals in one
vertical period to 512, which is one half the
number of effective scan lines.
If the BLANK changes when the Vsync
frequency is switched, the screen display may
be disturbed or brightness may change.
The screen display is restored to the normal
state later when the BLANK length is
constant again.
number of effective scan lines.
If the BLANK changes when the Vsync
frequency is switched, the screen display may
be disturbed or brightness may change.
The screen display is restored to the normal
state later when the BLANK length is
constant again.
-7-
(4) Connector
Specifications
The connector specification is shown below.
Please do not connect anything with the terminal NC.
(I) Signal connector CN1: DF13-20DP-1.25 V (tin-plated) (Maker: HIROSE DENKI)
Pin No.
Signal name
Pin No.
Signal name
1
RXIN0-
2
GND
3
RXIN0+
4
SCL
5
RXIN1-
6
GND
7
RXIN1+
8
SDA
9
RXIN2-
10
GND
11
RXIN2+
12
CPUGO
13
RXCLKIN-
14
PDPGO
15
RXCLKIN+
16
IRQ
17 RXIN3- 18 PDWN
19
RXIN3+
20
GND
[Conforming connector]
Housing: DF13-20DS-1.25C
Contact: DF-2630SCF
(II) Power Source Connectors for power supply(jig)
(a) Power input connector (b) Power supply output connector for system
CN61: B06P-VH
CN62:B03P-VH
(Maker: JST) (Maker: JST)
Pin No.
Symbol
Pin No.
Symbol
1 AC(L)
1 V
AUX
2 N.C
2 N.C
3 AC(N)
3 GND
4 N.C
5
N.C
6 F.G
[Conforming connector]
Housing: VHR-06N (or M)
Contact: SVH-21T-P1.1
(c) Power supply output connector for system
CN63: B5B-XH-A
(Maker: JST)
Pin No.
Symbol
1 Vpr1
2 N.C.
3 Vpr2
4 N.C.
5 GND
2 N.C.
3 Vpr2
4 N.C.
5 GND
[Conforming connector]
Housing: XHP-5
Contact:
SXH-001T-P0.6
[Conforming connector]
Housing: VHR-03N (or M)
Contact: SVH-21T-P1.1
-8-
(III)
Power Source Connectors
(a)
Power supply output
(b)
Power supply output
(c)
Power supply output
connector for system
connector for system
connector for system
CN6: B6B-PH-SM3-TB(JST) CN23: B10PS-VH(JST) CN33: B9PS-VH(JST)
Pin No.
Symbol
Pin No.
Symbol
Pin No.
Symbol
1 Vpr2
1 Va
1 Vcc
2 N.C.
2 N.C.
2 GND
3 GND
3 Vcc
3 GND
4 GND
4 GND
4 GND
5 N.C.
5 GND
5 GND
6 Vcc
6 GND
6 N.C.
7 N.C.
7 Vs
8 Vs
8 Vs
9 Vs
9 Vs
10 Vs
(d)
Power supply output
(e)
Power supply output
connector for system
connector for system
CN42: B7B-PH-SM3-TB(JST) CN52: B7B-PH-SM3-TB(JST)
Pin No.
Symbol
Pin No.
Symbol
1 Va
1 Va
2 N.C.
2 N.C.
3 N.C.
3 N.C.
4 GND
4 GND
5 GND
5 GND
6 N.C.
6 N.C.
7 Vcc
7 Vcc
[Conforming connector]
Housing: PHR-6
Contact: SPH-002T-P0.5L
[Conforming connector]
Housing: VHR-10N
Contact: SVH-21T-
P1.1
[Conforming connector]
Housing: VHR-9N
Contact: SVH-21T-P1.1
Contact: SVH-21T-P1.1
[Conforming connector]
Housing: PHR-7
Contact: SPH-002T-P0.5L
[Conforming connector]
Housing: PHR-7
Contact: SPH-002T-P0.5L
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