Sony KE-32TS2E / KE-32TS2U Service Manual ▷ View online
-3-
1.3.2 Display quality specification
Specification
Item NO
UA-1x UA-6x
UA-7x
Total number (subpixel)
1
15 or less
←
←
Density (subpixel/cm
2
)
2
2 or less
(However,1 continuousness or less)
(However,1 continuousness or less)
←
←
Non-lighting
cell defect
cell defect
Size(HxV) (subpixel)
3
1x2 or less,
Or 2x1 or less
Or 2x1 or less
←
←
Total number (subpixel)
4
6 or less
(each color 2 or less)
(each color 2 or less)
←
←
Non-extinguish
ing cell defect
ing cell defect
Density (subpixel/ cm
2
)
5
Each color 2 cells max
(However,1 continuousness or less)
(However,1 continuousness or less)
←
←
Flickering lighting cell defect
(sub pixel/ cm
(sub pixel/ cm
2
)
6
5 or less
←
←
Flickering cell
defect
defect
Flickering non-extinguishing cell
defect
defect
7
Number on inside of
Non-extinguishing cell defect
Non-extinguishing cell defect
←
←
High intensity
cell defect
cell defect
Twice or more bright point
8
0
←
←
White block of 10% load
[9 point](%)
[9 point](%)
9
20 or less
←
←
Brightness
variation
variation
In area adjacent 20mm
[White](%)
[White](%)
10
10 or less
←
←
Color variation
White block of 10% load
[9 point]
[9 point]
11
X: Average ±0.015
y: Average ±0.015
y: Average ±0.015
←
←
Note: It is made to give priority when there is a delivery specification according to the customer.
-4-
1.3.3 I/0 Interface Specification
(1) I/O signal
No.
Item
Signal Name
Number
of
signals
I/O
Form
Content of definition
Reflection
signal
Timing
Signal
signal
Timing
Signal
RXIN0-
RXIN0+
RXIN1-
RXIN1+
RXIN2-
RXIN2+
RXIN3-
RXIN3+
RXIN0+
RXIN1-
RXIN1+
RXIN2-
RXIN2+
RXIN3-
RXIN3+
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Input
LVDS
Differe
ntial
Differe
ntial
Differential serial data signal.
Input video and timing signals
after differential serial
conversion using a dedicated
transceiver.
The serial data signal is
transmitted seven times faster
than the base signal.
Input video and timing signals
after differential serial
conversion using a dedicated
transceiver.
The serial data signal is
transmitted seven times faster
than the base signal.
Clock
RXCLKIN-
RXCLKIN+
RXCLKIN+
1
1
1
Input
LVDS
Differe
ntial
Differe
ntial
Differential clock signal.
Input the clock signal after
differential conversion using a
dedicated transceiver.
The clock signal is transmitted
at the same speed as the base
signal.
Input the clock signal after
differential conversion using a
dedicated transceiver.
The clock signal is transmitted
at the same speed as the base
signal.
1
Display
Data
Data
Power down
Signal
Signal
PDWN 1
Input
LVTTL
Low: LVDS receiver
outputs are all L.
High: Input signals are
active.
SDA 1
I/O
Communication
SCL 1
I/O
LVTTL
(I
(I
2
C)
I
2
C bus serial data
communication signal.
Communication with the
control MPU of this product is
enabled.
Communication with the
control MPU of this product is
enabled.
CPUGO 1
Input
LVTTL
Low power consumption mode
of the control MPU of this
product is released.
of the control MPU of this
product is released.
PDPGO 1
Input
LVTTL
“High”:
This product is started.
(CPUGO=“High” Effective)
2
MPU
Comm
unicati
on/
Control
Comm
unicati
on/
Control
Control
IRQ 1
Output LVTTL
It changes into "Low" Î "High"
when this product enters the
undermentioned state.
1.Vcc/Va/Vs output decrease
2.Circuit abnormality detection
when this product enters the
undermentioned state.
1.Vcc/Va/Vs output decrease
2.Circuit abnormality detection
-5-
(2) LVDS Signal Definition and Function
A video signal (display data signal and control signal) is converted from parallel data to serial data with the LVDS
transmitter and further converted into four sets of differential signals before input to this product.
These signals are transmitted seven times faster than dot clock signals.
The dot clock signal is converted into one set of differential signals by the transmitter before input to this product.
The LVDS signal definition and function are summarized below:
transmitter and further converted into four sets of differential signals before input to this product.
These signals are transmitted seven times faster than dot clock signals.
The dot clock signal is converted into one set of differential signals by the transmitter before input to this product.
The LVDS signal definition and function are summarized below:
Signal name
Symbol
Number
of signals
Signal definition and function
RXIN0-
RXIN0+
1
1
1
Display data signal
R0,R1,R2,R3,R4,R5,G0
RXIN1-
RXIN1+
1
1
1
Display data signal
G1,G2,G3,G4,G5,B0,B1
RXIN2-
RXIN2+
1
1
1
Display data signal, Sync Signal, Control signal
B2,B3,B4,B5
_____ _____ _______
Hsync, Vsync, BLANK
_____ _____ _______
Hsync, Vsync, BLANK
Video signal
Timing signal
Transmission line
RXIN3-
RXIN3+
1
1
1
Display data signal, Control signal
R6,R7,G6,G7,B6,B7,PARITY
Clock transmission line
RXCLKIN-
RXCLKIN+
1
1
1
Clock signal
_____
DCLK
_____
DCLK
-6-
(3) Video Signal Definition and Function
The table below summarizes the definitions and functions of input video signals before
LVDS conversion.
LVDS conversion.
Item
Signal name
Number
of
signals
Input/
output
Signal definition and function
Video signal
(digital RGB)
(digital RGB)
DATA-R
DATA-G
DATA-B
DATA-G
DATA-B
8
8
8
8
8
Input
Display data signal
R7/G7/B7 is the highest intensity bit.
R0/G0/B0 is the lowest intensity bit.
R7/G7/B7 is the highest intensity bit.
R0/G0/B0 is the lowest intensity bit.
Data Clock
DCLK
1 Input
Display data timing signal: Data are read
when DCLK is low. DCLK is continuously
input.
when DCLK is low. DCLK is continuously
input.
Horizontal sync
signal
_____
Hsync
Hsync
1 Input
Regulates one horizontal line of data: Begins
control of the next screen when Hsync is
lowered.
control of the next screen when Hsync is
lowered.
Vertical sync
signal
_____
Vsync
Vsync
1 Input
Screen starts up control timing signal: Begins
control of the next screen when Vsync is
lowered.
Input the same frequency in both
odd-numbered and even-numbered fields.
control of the next screen when Vsync is
lowered.
Input the same frequency in both
odd-numbered and even-numbered fields.
Parity signal
PARITY
1
Input
This signal specifies the display field.
H: Odd-numbered field
L: Even-numbered field
L: Even-numbered field
Parity signal should be alternated in every
Vsync cycle. This signal is arbitrarily
reversed internally when there is no reversing
signal.
Vsync cycle. This signal is arbitrarily
reversed internally when there is no reversing
signal.
Original
Display
signal
(before
LVDS
transmitta
nce)
Display
signal
(before
LVDS
transmitta
nce)
Blanking signal
BLANK
1
Input
Display period timing signal.
H indicates the display period and L indicates
the non display period.
Note:
Set this timing properly like followings, as is
used internally for signal processing.
・
H indicates the display period and L indicates
the non display period.
Note:
Set this timing properly like followings, as is
used internally for signal processing.
・
Set the blanking period so that the number
of effective display data items in one
horizontal period is 852.
・
horizontal period is 852.
・
Set the number of blanking signals in one
vertical period to 512, which is one half the
number of effective scan lines.
If the BLANK changes when the Vsync
frequency is switched, the screen display may
be disturbed or brightness may change.
The screen display is restored to the normal
state later when the BLANK length is
constant again.
number of effective scan lines.
If the BLANK changes when the Vsync
frequency is switched, the screen display may
be disturbed or brightness may change.
The screen display is restored to the normal
state later when the BLANK length is
constant again.
Click on the first or last page to see other KE-32TS2E / KE-32TS2U service manuals if exist.