Sony KDL-60W840B / KDL-60W850B / KDL-60W855B / KDL-60W857B / KDL-70W830B / KDL-70W840B / KDL-70W850B / KDL-70W855B / KDL-70W856B / KDL-70W857B Service Manual ▷ View online
Chassis:
RB2G,
HM
93
Chassis:
RB2G,
HM
A BOARD SCHEMATIC DIAGRAM (17 OF 17)
TS
AYU2-BROWNIE_I/F
GPIO
TSIO
AYU2L-BROWNIE_I/F
G
G
DESCRIPTION
A
4
H
11
MODEL
B
5
I
12
ORIGINAL
C
6
J
13
SHEET
D
7
K
14
1
E
8
L
15
2
F
9
PART NO.
16
3
G
10
BAX_L BOARD
AYU2-BROWNIE I/F
ALL resistors are in ohms,W unless otherwise noted.
ALL capacitors are in uF(p:pF)unless otherwise noted.
ALL capacitors are in uF(p:pF)unless otherwise noted.
2014/02/27
20:15
RB2_BAX_L_CVDA_270214.cir/018.sht
5004103813
RB2
18/18
To PCB System
DAUIA_BCK_CLK
TS_PI_DAT_0
009:8C
+3.3V_MAIN
DAUOD_MCLK_CLK
CL8507
SPIC_DI
0
R8555
TSI_EN
018:11D
XX
R8561
TSIO_STRT
009:6D
DMD_CLK_ENABLE2
X_ADAC_MUTE_HPLO
GND_D
TSIE_DAT
018:6D
I2CB_SCL
TSI_DAT
018:11D
TU1_TS_VALID
009:8D
XX
R8541
DAUIA_DAT_0
TSIO_DAT_4
018:7C
DAUOD_LRCK_CLK
GND_D
X_SYSTEM_RST
DAUOC_MCLK_CLK
DAUOC_MCLK_CLK
DAUOC_LRCK_CLK
TS_PI_DAT_1
009:6J
XX
R8510
TSI_EN
018:6C
VFE_DIO_D6_1
XX
R8557
0
R8552
RB8514
XX
2
1
4
3
6
5
8
7
GND_D
SPIC_CS
DAUIA_LRCK_CLK
XX
R8563
XX
R8560
CL8502
+3.3V_MAIN
TSI_CK
018:11D
TS_PI_DAT_2
009:6J
CL8504
XX
R8515
SPID_CK
VFE_DIO_D9_4
CL8517
XX
R8554
SPID_DI
DAUOC_BCK_CLK
CL8506
SPIC_CK
XX
R8522
DAUOD_DAT_0
018:6G
TSIO_CK
009:6D
CL8503
DMD_RESET1
DAUOD_BCK_CLK
CL8511
VFE_DIO_D5_0
X_ADAC_MUTE_SCART
XX
R8509
470
R8506
XX
R8548
2.2k
R8542
TSIO_DAT_0
009:6C
DMD_CLK_ENABLE1
XX
R8569
TSIO_DAT_6
018:11D
SPIC_DI
TSIE_STRT
018:6D
TSIE_CK
018:11E
DAUOD_LRCK_CLK
018:6F
RB8511
XX
2
1
4
3
6
5
8
7
TSI_DAT
018:6D
TSI_STRT
018:6C
DAUOA_DAT0_HSS
012:7G;012:9G
TU1_TS_CLK
009:10D
DMD_RESET2
DAUOC_DAT_0
018:6F
DAUOD_MCLK_CLK
CL8516
XX
R8556
XX
R8545
X_ADAC_MUTE_HPLO
DAUIA_DAT_0
I2C_CCP_SCL
DAUIA_BCK_CLK
CCP_INT
GND_D
TSIO_EN
009:6C
DAUOC_BCK_CLK
CL8515
+3.3V_MAIN
I2C_CCP_SCL
CL8505
TS_PI_DAT_3
009:6J
DAUIA_LRCK_CLK
SPID_CK
XX
R8559
0
R8514
TS_PI_VALID
009:8C
I2C_CCP_SDA
SPIC_CS
XX
R8512
PICTURE_MUTE_INT
XX
R8513
XX
R8520
X
X
R8534
GND_D
XX
R8562
TSIE_DAT
018:11E
DAUOD_DAT_0
XX
R8501
CL8512
XX
R8568
I2C_CCP_SDA
DAUOC_DAT_0
XX
R8516
VFE_DIO_DEN
TSIO_DAT_5
009:6J
4.7k R8547
C8502
XX
C8504
XX
C8507
XX
CL8509
TSIE_CK
018:6D
I2CB_SDA
XX
R8507
SPIC_DO
XX
R8524
TSIO_DAT_6
018:7C
C8508
XX
XX
R8553
TSIO_DAT_4
018:11D
C8506
XX
TSI_STRT
018:11D
XX
R8511
CL8508
TS_PI_CLK
009:8D
XX
R8558
VFE_DIO_D8_3
D+1.1V
DAUOD_BCK_CLK
018:6F
SPIC_CK
CL8514
CL8513
DAUO_SPDIFOP_HSS
012:7H;009:8J
SPIC_DO
4.7k R8546
TS_PI_SYNC
009:8D
2.2k
R8535
XX
R8525
2.2k
R8536
XX
R8508
X_ADAC_MUTE_SCART
VFE_DIO_CLK
XX
R8549
VFE_DIO_D7_2
CL8510
SPID_DI
DAUOC_LRCK_CLK
XX
R8537
RB8510
XX
2
1
4
3
6
5
8
7
TSIE_EN
018:6D
XX
R8533
CL8500
GND_D
CL8501
TSI_CK
018:6C
D+1.1V
RB8501
22
2
1
4
3
6
5
8
7
0
R8502
1005
CHIP
C8500
11p
C8501
10p
VFE_DIO_D7_2
VFE_DIO_D8_3
VFE_DIO_D9_4
VFE_DIO_CLK
VFE_DIO_DEN
VFE_DIO_D5_0
VFE_DIO_D6_1
X_AUDIO_MUTE_SCART
X_AUDIO_MUTE_SPHPLO
XX
R8550
MS_INS_X
004:15H
XX
R8551
MS_PON
004:15H
XX
R8577
XX
R8578
+3.3V_MAIN
IC9001
CXD4743GB-T8
F4
TS_SI_CLK
G3
TS_SI_SYNC
G4
TS_SI_VALID
F3
TS_SI_DATA
F5
TSPLLAVD11
G5
TSPLLAVS11
D1
TS_PI_CLK
D2
TS_PI_SYNC
D3
TS_PI_VALID
C1
TS_PI_DATA0
C2
TS_PI_DATA1
B1
TS_PI_DATA2
B2
TS_PI_DATA3
A2
TS_PI_DATA4
C3
TS_PI_DATA5
B3
TS_PI_DATA6
A3
TS_PI_DATA7
A4
TS_SO1_CLK
B5
TS_SO1_SYNC
C5
TS_SO1_VALID
A5
TS_SO1_DATA
C4
TS_SO2_CLK
D5
TS_SO2_SYNC
D4
TS_SO2_VALID
B4
TS_SO2_DATA
IC9001
CXD4743GB-T8
F2
SCL_C
E2
SDA_C
E1
SCL_D
E3
SDA_D
C10
AFE_MCLK_A
D10
AFE_IBCK_A
D9
AFE_ILRCK_A
D8
AFE_IDATA_A
D7
AFE_MCLK_B
C8
AFE_IBCK_B
C9
AFE_ILRCK_B
A7
AFE_IDATA_B
B6
AFE_OBCK
A6
AFE_OLRCK
C6
AFE_OD
C7
AFE_IINTR_MUTE_A
B7
AFE_IINTR_MUTE_B
B16
SPI1_DIN
A16
SPI1_DOUT
B15
SPI1_CS
C15
SPI1_CLK
A15
SPI2_DOUT
E15
SPI2_CS
C14
SPI2_CLK
B13
CCP_CLK
A13
CCP_DATA_EN
D15
SDVBS_4
D14
SDVBS_3
E14
SDVBS_2
D13
SDVBS_1
E13
SDVBS_0
D16
CCP_INTERP1
B14
CCP_INTERP2
A14
CCP_INTERP3
IC9001
CXD4743GB-T8
K1
GPIO0
K2
GPIO1
H5
GPIO2
H2
GPIO3
H3
GPIO4
H4
GPIO5
H1
GPIO6
V1
XTALO
W1
XTALI
F1
OSCEN_X
G2
RST_X
V3
CKTESTIN
U3
CKTESTOUT
T3
TESTEN
T4
TESTMODE
E12
VDDQ
G1
SLVADR0
MS_SCK
004:15G
0
R8538
0
R8539
0
R8540
MS_DATA
004:15G
MS_BS
004:15G
XX
R8543
+3.3V_MAIN
XX
R8544
TSIE_STRT
018:11E
TSIE_EN
018:11E
C8509
0.01
50V
X7R
1005
XX
R8517
XX
R8518
XX
R8519
XX
R8579
XX
R8580
XX
R8581
XX
R8582
XX
R8590
XX
R8591
XX
R8592
XX
R8593
XX
R8601
XX
R8602
XX
R8603
XX
R8604
TU1_TS_SYNC
009:8D
TU1_TS_DATA0
009:8D
TSIO_DAT_7
018:11D
TS_PI_DAT_5
009:6J
TSIO_DAT_2
009:6J
TSIO_DAT_3
009:6J
TSIO_DAT_1
009:6J
TSIO_DAT_7
018:7C
X_BROWNIE_RST
XX
R8526
47
R8531
1/16W
CHIP
5%
47
R8530
RB8504
47
2
1
4
3
6
5
8
7
RB8505
47
2
1
4
3
6
5
8
7
C8510
XX
C8511
XX
*IC9000
CXD4748GB
AF1
TSIO_CK/GPIO_52/SCI_CK/SCI_TDA_CLK
AF2
TSIO_STRT/GPIO_54/SCI_DI/SCI_DIO
AF3
TSIO_EN/GPIO_53/SCI_RST/SCI_RST
AG1
TSIO_DAT_0/GPIO_55/SCI_DOEN
AG2
TSIO_DAT_1/GPIO_56/SCI_DET/SCI_DET
AG3
TSIO_DAT_2/GPIO_57/SCI_VEN/SCI_CMDVCC
AH1
TSIO_DAT_3/GPIO_58/SCI_OCD/SCI_CLKDIV
AJ1
TSIO_DAT_4/GPIO_59
AH2
TSIO_DAT_5/GPIO_60
AJ2
TSIO_DAT_6/GPIO_61
AK2
TSIO_DAT_7/GPIO_62
AJ13
TSI_CK
AH14
TSI_STRT
AG14
TSI_EN
AJ14
TSI_DAT
AJ12
TSIE_CK
AG13
TSIE_STRT
AH13
TSIE_EN
AK12
TSIE_DAT
*IC9000
CXD4748GB
AD3
I2C_CCP_SDA
AE3
I2C_CCP_SCL
AJ18
DAUOC_MCK
AH18
DAUOC_BCK
AK17
DAUOC_LRCK
AJ17
DAUOC_DAT_0
AH17
DAUOD_MCK
AJ16
DAUOD_BCK
AG17
DAUOD_LRCK
AH16
DAUOD_DAT_0
AH15
DAUIA_BCK
AJ15
DAUIA_LRCK
AK14
DAUIA_DAT_0
AK15
X_ADAC_MUTEC
AG16
X_ADAC_MUTED
AJ22
MS_BS/SPIC_DO
AK21
SPIC_DI
AK22
MS_DATA/SPIC_CS
AH22
MS_SCK/SPIC_CK
AJ21
SPID_DI
AH21
SPID_CK
AK20
VFE_DIO_CLK
AJ20
VFE_DIO_DEN
AH20
VFE_DIO_D9_4
AK19
VFE_DIO_D8_3
AJ19
VFE_DIO_D7_2
AH19
VFE_DIO_D6_1
AK18
VFE_DIO_D5_0
AG5
X_AUDIO_MUTEC
AF4
X_AUDIO_MUTED
A4
MS_INS_X/GPIO_37
C5
MS_PON/GPIO_36
47
R8570
47
R8571
47
R8572
RB8517
47
2
1
4
3
6
5
8
7
XX
R8565
RB8518
47
2
1
4
3
6
5
8
7
X8501 41MHz
181447511
1
2
*C8503
XX
*C8505
XX
RB8515 0
2
1
4
3
6
5
8
7
Brownie Audio DAC Mute
DAUOD_DAT_0 = STRAP_G[11](InternalPD)
VFE digital :
The reserve C-lands for EMI.
The reserve C-lands for EMI.
DAUOC_DAT_0 = STRAP_G[8](InternalPD)
□ DAUOD_BCK = STRAP_G[10](InternalPD)
->Strap setting at PERI(STBY)
For Analog Input
Reserve for interference,
the value is TBD.(2012/8/9)
the value is TBD.(2012/8/9)
1:debug_mode_on
SPID_CK = STRAP_G[22](InternalPD)
VFE digital :
Please put VFE bus on Layer-3 for EMI/interfarence C/M.
R8570-R8576:
if possible on PWB design, please put close to Brownie(IC9001).
Please put VFE bus on Layer-3 for EMI/interfarence C/M.
R8570-R8576:
if possible on PWB design, please put close to Brownie(IC9001).
*** Strap Setting ***
For CI Transfer
1:VDDO=3.3V
0:default pin assign
For Software Use (PCB type ID)
Slice Data from Brownie
PCBID = b’01
For board detection of Ryu SW (RB2 Ayu2L)
For board detection of Ryu SW (RB2 Ayu2L)
□ DAUOD_LRCK = STRAP_G[9](InternalPD)
DAUOA_DAT_0 = STRAP_G[5](InternalPD)
0:VDDO=1.8V
0:debug_mode_off
DAUOC_LRCK = STRAP_G[6](InternalPD)
DAUO_SPDIF_0 = STRAP_G[12](InternalPD)
SD Video
AYU2 -> Brownie :
Brownie -> AYU2 :
AYU2 -> Brownie :
Brownie -> AYU2 :
For HP/Line Out
BROWNIE
RawNAND PowerSetting
AYU2
C : SP/HP Out Mute
D : SCART Out Mute
D : SCART Out Mute
FEIP ES EVA mode (for TSB use)
*** Strap Setting ***
*** Strap Setting ***
For SCART Out
1:FEIP_GPIO pin assign
DAUOC_BCK = STRAP_G[7](InternalPD)
To BCAS Connector
*** Strap Setting ***
*** Strap Setting ***
0:Ether REFclock output mode
1:Ether REFclock input mode
1:Ether REFclock input mode
0:Normal mode
1:JIG mode
1:JIG mode
Ether REFclock setting
JIG mode setting
Debug mode setting
X_ADAC_MUTED= STRAP_G[1] (InternalPD)
reserved
0:P/M/S=5/0X54/0 806.4MHz
1:P/M/S=5/0X91/1 696.0MHz
1:P/M/S=5/0X91/1 696.0MHz
PLL_CPU setting
X_ADAC_MUTEC = STRAP_G[0] (InternalPD)
*** Strap Setting ***
Memory Stick
Tuner Board I/F connector
To avoid stub connection of W-tuner Serial-TS line and mount variation in this board,
make return path to Tuner Board
make return path to Tuner Board
X_SCI_DET
SCI_VEN
X_SCI_OCD
To Brownie via TunerBoard
TSIO_DAT_5 =TS_PI_DAT_5 =POL_SW
TSIO_DAT_5 =TS_PI_DAT_5
=POL_SW
=POL_SW
In PWB Design, please put CL8517 at B-side
In PWB Design, please put CL8516 at B-side
2013/11/29 15:29
[ SOC ]
┌────────┬────────┬────────┐
│ │60 │60AVS │
├────────┼────────┼────────┤
│IC9000 │CXD4748GB │CXD4748GB-1 │
└────────┴────────┴────────┘
2013/11/29 15:29
[ SEGMENT ]
┌────────┬────────┬────────┐
│ │HE │HM │
├────────┼────────┼────────┤
│C8503 │XX │3300p │
│ │ │50V │
│ │ │X7R │
│ │ │ │
├────────┼────────┼────────┤
│C8505 │XX │7p │
│ │ │50V │
│ │ │CH │
│ │ │ │
└────────┴────────┴────────┘
Chassis:
RB2G,
HM
94
Chassis:
RB2G,
HM
TUS BOARD SCHEMATIC DIAGRAM (1 OF 8)
F
5
C
2
A
D
4
A
1
H
E
E
12
DRAWNING
(TYPE D42)
G
B
D
11
SONY STANDARD
’90.10
8
A2
C
10
I S S U E D ’ . .
7
H
B
F
9
6
G
3
mm
X
SUFFIX
DESCRIPTION
’ . .
:
R E V I S I O N
6
FAMILY
-
3
PART NO.
DRAWN BY
’ . .
SCALE
D A T E
X
ORIGINAL
MODEL
MODEL
-
X
PART NO.
PLANNED BY
’ . .
ANGLE
ECN-NO.
5
FINISH(COLOR)
-
2
SHEET
CHECKED BY
’ . .
UNIT
X
MATERIAL(COLOR)
-
X
TENTATIVE
’ . .
TOLERANCE
REPL.
( J )
APPROVED BY
-
1
MODEL
’ . .
USED ON
4
( E )
HISTORY
-
X COUNT
SIGN.
X
RANK
A L L r e s i s t o r s a r e i n o h m s , W u n l e s s o t h e r w i s e n o t e d .
A L L c a p a c i t o r s a r e i n u F ( p : p F ) u n l e s s o t h e r w i s e n o t e d .
TO THE LOCAL PURCHASING DEPARTMENT OF SONY. THE REPRODUCTION, DISTRIBUTION AND UTILIZATION OF THIS DOCUMENT AS WELL AS THE COMMUNICATION OF ITS CONTENTS TO OTHERS WITHOUT EXPRESS AUTHORIZATION
THIS DOCUMENT IS THE PROPRIETARY PROPERTY OF SONY. ITS USE IS AUTHORIZED ONLY FOR RESPONDING TO A REQUEST FOR QUOTATION, OR FOR THE PERFORMANCE OF WORK FOR SONY. ALL QUESTIONS MUST BE REFERRED
IS PROHIBITED. OFFENDERS WILL BE HELD LIABLE FOR THE PAYMENT OF DAMAGES. ALL RIGHTS RESERVED IN THE EVENT OF THE GRANT OF A PATENT, UTILITY MODEL OR DESIGN. COPYRIGHT RESERVED.
YYYY/MM/DD
HH:MM
COVER SHEET
1 / 7
RB2
Tuner BOARD
TUS
0 0 1 . s h t
0 0 2 . s h t
0 0 3 . s h t
0 0 4 . s h t
0 0 5 . s h t
0 0 6 . s h t
0 0 7 . s h t
0 0 2 . s h t
0 0 3 . s h t
0 0 4 . s h t
0 0 5 . s h t
0 0 6 . s h t
0 0 7 . s h t
2000 - 2009
2100 - 2999
7600 - 7899
6200 - 6399
3100 - 3199
9700 - 9899
2100 - 2999
7600 - 7899
6200 - 6399
3100 - 3199
9700 - 9899
KAMA KamaAzira.Kamil@ap.sony.com
KAMA KamaAzira.Kamil@ap.sony.com
FAREEZ FareezEzwan.MohdSaniAriffin@ap.sony.com
SYAFIQ MohamadSyafiq.Salahuddin@ap.sony.com
AZMIR azmir.hajiabdghani@ap.sony.com
KAMA KamaAzira.Kamil@ap.sony.com
KAMA KamaAzira.Kamil@ap.sony.com
FAREEZ FareezEzwan.MohdSaniAriffin@ap.sony.com
SYAFIQ MohamadSyafiq.Salahuddin@ap.sony.com
AZMIR azmir.hajiabdghani@ap.sony.com
KAMA KamaAzira.Kamil@ap.sony.com
Cover Sheet
T u n e r , D e m o d . T U N E R
L N B P o w e r T U N E R
S y s t e m G E N S Y S T E M
C I D I G I T A L I N T E R F A C E
V i d e o T e r m i n a l s V I D E O
Card Edge Connector TUNER
T u n e r , D e m o d . T U N E R
L N B P o w e r T U N E R
S y s t e m G E N S Y S T E M
C I D I G I T A L I N T E R F A C E
V i d e o T e r m i n a l s V I D E O
Card Edge Connector TUNER
DATE: 05-DEC-2013(11.30 A.M)
DIB APPLIED UNTIL: DIB 552
3.7 - TUNER BOARD SCHEMATIC
Click on the first or last page to see other KDL-60W840B / KDL-60W850B / KDL-60W855B / KDL-60W857B / KDL-70W830B / KDL-70W840B / KDL-70W850B / KDL-70W855B / KDL-70W856B / KDL-70W857B service manuals if exist.