Sony KDL-20G3000 / KDL-20G3030 Service Manual ▷ View online
DD
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10
A
B
C
D
E
F
G
H
J
I
K
L
M
N
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
11
10
11
22
21
22
R
Q
O
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EE
FF
S
T
U
V
W
X
Y
Z
AA
BB
CC
DD
A
B
C
D
E
F
G
H
J
I
K
L
M
N
12
13
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16
17
18
19
20
21
20
18
19
17
15
16
14
12
13
Q
R
S
T
U
V
W
X
Y
AA
TP7215
10k
*R7226
*R7201
XX
100
*R7231
JL7217
RESET_N
1k
*R7235
FE_NAND_ALE
XX
*R7216
10k
*R7203
TP7213
FE_NAND_CLE
100p
*C7217
TP7207
68
*RB7205
1
2
3
4
5
6
7
8
470
*R7206
JL7207
GND_1
TP7202
TP7220
JL7202
100p
*C7215
JL7205
JL7220
0uH
*FB7200
100
*RB7207
1
2
3
4
5
6
7
8
1k
*RB7204
2
1
4
3
6
5
8
7
TP7221
470
*R7200
100
*RB7211
1
2
3
4
5
6
7
8
RT1N141M-TP-1
Q7203
FE_DBA0,FE_DBA1,FE_DCASB,FE_DCKE,FE_DCLK,FE_DCLKB,FE_DCSB,FE_DQM0,FE_DQM1,FE_DQS0,FE_DQS1,FE_DRASB,FE
_DVREF,FE_DWEB
1005
1/16W
CHIP
5%
R7243
10k
0 . 0 1
*C7231
TP7205
470
*R7207
GND_1
FE_RDATA[0-7]
XX
*R7210
FE_FOEB
TP7210
TP7201
*C7219
0 . 1
FE_NAND_RBB
XX
*C7230
JL7209
0 . 1
*C7212
S
2SK2036(TE85L)
Q7201
15uH
*L7200
XX
*R7214
1k
*R7204
XX
*R7225
TP7216
100
*R7232
0uH
*FB7201
100
*RB7210
1
2
3
4
5
6
7
8
FE_CVBS
GND_1
68
*RB7212
1
2
3
4
5
6
7
8
TP7209
*C7222
0 . 1
JL7223
0 . 1
*C7203
XX
*R7211
4.7k
*R7208
*X7200
XX
*R7215
RF_DIGITAL
68
*RB7206
1
2
3
4
5
6
7
8
100
*R7229
*Q7200
100p
*C7213
0 . 1
*C7200
0.1
*C7208
XX
*R7205
JL7203
FE_DQ[0-15]
TP7200
*R7224
10k
10k
*R7221
100
*RB7208
1
2
3
4
5
6
7
8
TP7218
*C7220
0 . 1
TP7211
*R7202
1k
GND_1
TP7227
SCL
0 . 1
*C7210
GND_1
FE_CLK27M
100p
*C7216
1005
1/16W
CHIP
5%
R7242
10k
TP7206
TP7208
JL7216
JL7218
100
*R7230
SCL_EMMA
0uH
*FB7202
FE_FTV_CONFIG0
68
*R7228
XX
*R7222
JL7210
1
*C7201
0 . 1
*C7226
GND_1
100p
*C7214
SDA_EMMA
*C7218
0 . 1
100
*R7219
TP7219
27p
*C7228
0 . 0 0 1
*C7205
68
*R7217
FE_FTV_CONFIG2
JL7219
FE_DADD[0-12]
68
*RB7213
1
2
3
4
5
6
7
8
JL7208
GND_1
GND_1
TP7224
TP7204
0 . 1
*C7227
JL7204
TP7222
FE_PWMOUT
TP7225
100
*RB7209
1
2
3
4
5
6
7
8
XX
*R7209
GND_1
XX
*C7207
0 . 1
*C7202
JL7211
8
7
6
5
4
3
2
1
*IC7202
X1
NC
VIN
GND
CLK
VDD
PD
X2
0 . 1
*C7221
TP7217
JL7206
XX
*R7220
*R7234
220
48
9
53
56
1
49
50
51
2
55
54
52
345678
47
10
46
45
44
43
42
11
12
13
14
15
41
40
39
38
37
36
35
16
17
18
19
20
21
22
34
33
23
24
32
25
31
30
29
26
27
28
57
58
59
60
61
62
63
64
65
66
*IC7201
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BS0
BS1
A10
A0
A1
A2
A3
DQ15
VSS
A4
A5
A6
A7
A8
A9
A11
A12
NC
CKE
CLK
CLK
UDM
VSS
VREF
NC
UDQS
VSSQ
NC
DQ8
VDDQ
DQ9
DQ10
VSSQ
DQ11
DQ12
VDDQ
DQ13
DQ14
VSSQ
VSS
VDD
FE_FTV_CONFIG1
FE_RADD[19-25]
GND_1
TP7203
TP7223
XX
*R7212
FE_FWEB
TP7226
SDA
GND_1
RT1P431M-TP-1
Q7204
100
*R7218
47
*R7233
JL7221
10k
*R7223
68p
*C7229
*C7223
0 . 1
0 . 1
*C7204
XX
*R7213
FE_FCSB0
XX
*C7206
TP7214
GND_1
TP7212
GND_1
1k
*R7227
100
*C7225
220
*R7246
0 . 1
*C7234
0.22F
*C7236
SCL
47
*C7235
1p
*C7233
KEY
JL7222
*D7200
*R7244
3 . 3 k
1
0
9876
5
4
3
2
1
*IC7203
32KOUT
SCL
SDA
INTRC
VSS
INTRA
INTRB
OSCOUT
OSCIN
VDD
SDA
1p
*C7232
2
3
4
1
*X7201
4.7
*C7211
4 . 7
*C7224
4 . 7
*C7209
XX
R7236
100
*R7237
100
*R7238
100
*R7241
R7239
XX
R7240
XX
XX
R7245
S
2SK2036(TE85L)
Q7202
XX
*C7237
GND_1
1k
RB7202
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
1k RB7200
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
FE_CI_TSD[0-7]
48
43
6
5
46
4
3
2
1
47
45
44
42
41
37
38
39
40
12
10
11
9
8
7
36
31
32
33
34
35
18
17
16
15
14
13
30
29
28
27
26
25
24
23
22
21
20
19
*IC7200
NC
NC
NC
NC
NC
NC
RB
FOE
CE
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O1
I/O2
IO/3
IO/4
NC
NC
NC
VSS
VCC
LOCKPRE
NC
NC
IO/5
IO/6
IO/7
IO/8
NC
NC
NC
NC
FE_DADD[7]
FE_DQ[2]
FE_DQ[15]
FE_DCLKB
FE_DQ[6]
FE_RDATA[3]
FE_DADD[1]
FE_DQ[4]
GND_1
FE_DQ[3]
FE_RADD[23]
GND_1
GND_1
FE_DQ[12]
FE_RDATA[4]
FE_DADD[12]
FE_DCKE
FE_DWEB
FE_DADD[6]
FE_RDATA[5]
FE_DADD[0]
FE_DADD[3]
FE_DQ[7]
FE_DVREF
FE_DBA0
GND_1
FE_DADD[10]
FE_DCLK
FE_DVREF
GND_1
FE_DQ[10]
GND_1
FE_RADD[21]
FE_RDATA[0]
FE_DQS1
FE_RADD[24]
GND_1
FE_DQ[11]
FE_DCSB
FE_DQ[1]
FE_RADD[19]
FE_DQM0
FE_RDATA[2]
FE_RADD[22]
FE_DADD[2]
FE_RDATA[7]
FE_DADD[9]
GND_1
FE_DADD[5]
FE_RDATA[6]
FE_RADD[25]
FE_DADD[8]
FE_DBA1
FE_DCASB
FE_DQ[13]
FE_RADD[20]
3.3V_MAIN
GND_1
FE_DRASB
GND_1
GND_1
FE_DQM1
FE_DQ[8]
FE_DADD[11]
FE_DADD[0-12]
FE_DQ[0]
FE_DQ[5]
FE_DQ[9]
FE_DQS0
FE_DQ[14]
FE_DADD[4]
FE_RDATA[1]
FE_RDATA[0]
FE_RDATA[4]
FE_RDATA[5]
FE_RDATA[3]
FE_CI_TSD[3]
FE_RDATA[6]
FE_CI_TSD[7]
FE_RDATA[1]
FE_CI_TSD[5]
FE_CI_TSD[6]
FE_RDATA[2]
FE_CI_TSD[1]
FE_CI_TSD[4]
FE_RDATA[7]
FE_CI_TSD[0]
FE_CI_TSD[2]
PLACE R7201 &
R7202 ADJACENT
R7202 ADJACENT
BOARD VERSION RESISTORS - MOUNT ON
SIDE-A
SIDE-A
0
PLEASE PLACE COMPONENTS IN
FTV_CONFIG2
DDR SDRAM
NAND FLASH
LEAVE N.C. SO NOT USED
LAYOUT NOTE:-
REMOVE GND PLANE AROUND AND UNDERNEATH IC7202
AND X7200 INCLUDING TRACKS FROM XTAL TO IC.
REMOVE GND PLANE AROUND AND UNDERNEATH IC7202
AND X7200 INCLUDING TRACKS FROM XTAL TO IC.
EJTAG_MODE
0.5%
FTV_CONFIG0
0
0
OPTION #2
DINT_EN
TO FORCE "BOOT FROM MEMORY STICK",
CONNECT (SHORT) TP7207 TO TP7208, OR
CONNECT (SHORT) JL7200 TO JL7201
CONNECT (SHORT) TP7207 TO TP7208, OR
CONNECT (SHORT) JL7200 TO JL7201
NOTE PIN 6 IS NOT GND ON SAMSUNG
NAND FLASH, ONLY TOSHIBA
NAND FLASH, ONLY TOSHIBA
FTV_CONFIG1
BOARD VERSION RESISTORS - MOUNT ON
SIDE-B WITH JL’S ON SIDE-B
SIDE-B WITH JL’S ON SIDE-B
VIDEO AMPS/BUFFERS
PLACE THESE CLOSE TO PIN 49 OF IC
NANDCS
PCIMODE
27MHZ CLOCK
RDATA[0] = 1 = ENDIAN = Big Endian
RDATA[2:1] = 10 = MRGMODE1-0 = Full merge & All bytes
RDATA[3] = -- = RESERVED
RDATA[5:4] = 10 = VRCLKSEL1-0 = 187MHz
RDATA[8:6] = 101 = MCLKSEL2-0 = 166MHz
RDATA[9] = 1 = ROMBEND = Big Endian
RDATA[10] = 1 = BWSEL = 8bit
RDATA[11] = 1 = MINIBOOT = use miniboot
RDATA[13:12] = 11 = BOOTSEL1-0 = Nand, then Memory Stick
RDATA[15:14] = 00 = BOOT_NAND_SEL1-0 = <256mbit
RADD[25] = 1 = EJTAG_MODE = EJTAG
RADD[24] = 0 = DINT_EN = disable
RADD[23] = 1 = DSYSELB = main only
RADD[22] = 1 = PCIMODE = host
RADD[21:20] = 00 = PCI_SIZE1-0 = 32Mbyte
RADD[19] = 0 = NANDCS = CS0
RDATA[2:1] = 10 = MRGMODE1-0 = Full merge & All bytes
RDATA[3] = -- = RESERVED
RDATA[5:4] = 10 = VRCLKSEL1-0 = 187MHz
RDATA[8:6] = 101 = MCLKSEL2-0 = 166MHz
RDATA[9] = 1 = ROMBEND = Big Endian
RDATA[10] = 1 = BWSEL = 8bit
RDATA[11] = 1 = MINIBOOT = use miniboot
RDATA[13:12] = 11 = BOOTSEL1-0 = Nand, then Memory Stick
RDATA[15:14] = 00 = BOOT_NAND_SEL1-0 = <256mbit
RADD[25] = 1 = EJTAG_MODE = EJTAG
RADD[24] = 0 = DINT_EN = disable
RADD[23] = 1 = DSYSELB = main only
RADD[22] = 1 = PCIMODE = host
RADD[21:20] = 00 = PCI_SIZE1-0 = 32Mbyte
RADD[19] = 0 = NANDCS = CS0
0.5%
0
DSYSELB
STRAP PINS
OPTION #3
OPTION #1
0
0
0
PLACE THESE CAPACITORS CLOSE TO IC PINS.
0
THIS BOX IN SAME AREA ON PWB
S/W OPTION SELECT RESISTORS
PCI_SIZE1
PCI_SIZE0
0
ROMBEND
ENDIAN
VRCLKSEL0
BOOT_NAND_SEL_0
MCLKSEL0
MRGMODE1
MCLKSEL1
RESERVED
BWSEL
VRCLKSEL1
MINIBOOT
MCLKSEL2
BOOTSEL0
MRGMODE0
BOOTSEL1
BOOT_NAND_SEL_1
3.3V_MAIN
3.3V_MAIN
3.3V_MAIN
3.3V_MAIN
3.3V_MAIN
3.3V_MAIN
3.3V_MAIN
3.3V_MAIN
3.3V_STBY
5V_MAIN
FE_+2V5_DDR
B2
2B/13
B2.-SE2
B2
2A/13
COMPONENTS MARKED AS XX REFER TO PARTS LIST, WILL ONLY BE LISTED IF FITTED
B2
2C/13
B2
2D/13
~ B2 Board Schematic Diagram [ Main Microcontroller, Scarts, AV Side & Component Input ] Page 2/13 ~
Ver 2.0
DD
CC
BB
O
P
EE
FF
Z
10
A
B
C
D
E
F
G
H
J
I
K
L
M
N
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
11
10
11
22
21
22
R
Q
O
P
EE
FF
S
T
U
V
W
X
Y
Z
AA
BB
CC
DD
A
B
C
D
E
F
G
H
J
I
K
L
M
N
12
13
14
15
16
17
18
19
20
21
20
18
19
17
15
16
14
12
13
Q
R
S
T
U
V
W
X
Y
AA
*R7322
100
3.3V_MAIN
FE_CI_TSCLK,FE_CI_TSSYNC,FE_CI_TSVAL
*R7304
10k
FE_IOWRB_FWEB
*R7330
10k
GND_1
*C7309
0 . 1
*R7302
10k
*R7321
100
XX
*R7307
FE_CI1_CE1B
FE_BUF_DIR
*C7311
0 . 1
*FB7300
0uH
FE_CI1_CD2B
FE_CI1_PWR_EN
A1
B1
A2
B2
A3
B3
A4
A5
A6
B4
B5
B6
A7
B7
A8
B8
A9
B9
A10
B10
A11
B11
A12
B12
A13
B13
A14
B14
A15
B15
A16
B16
A17
B17
A18
B18
A19
B19
A20
B20
A21
B21
A22
B23
B27
B24
B25
A28
B28
A29
B29
A24
A25
A26
A23
A30
B30
B26
A27
A32
A33
A31
B31
B33
B32
B22
A34
B34
179376921
*CN7300
GND
D3
D4
D5
D6
D7
CE1#
A10
OE#
A11
A9
A8
A13
A14
WE#
IREQ#
VCC
VPP1
MIVAL
MCLKI
A12
GND
CD1#
MDO3
MDO4
MDO5
MDO6
MDO7
CE2#
VS1#
IORD#
IOWR#
MISTRT
MDI0
MDI1
MDI2
MDI3
VCC
VPP2
MDI4
MDI5
MDI6
A7
MDI7
A6
MCLKO
A5
RESET
A4
WAIT#
A3
INPACK#
A2
REG#
A1
MOVAL
A0
MOSTRT
D0
MDO0
D1
MDO1
D2
MDO2
IOIS16#
CD2#
GND
GND
FE_IOWRB
*FB7308
0uH
*C7315
0 . 1
*C7303
1000p
FE_CI1_VS1B
*R7323
10k
14
13
12
11
10
9
8
7
1
2
3
4
5
6
*IC7303
1A
1Y
2A
2Y
3A
3Y
GND
4
Y
4A
5Y
5A
6Y
6A
VCC
*C7306
0 . 1
20
19
18
17
16
15
14
13
12
11
12345678
91
0
*IC7307
OE1
A0
A1
A2
A3
A4
A5
A6
A7
GND
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
OE2
VCC
*R7308
100
*FB7306
0uH
*R7319
47
*R7313
47
*C7304
0 . 1
20
19
18
17
16
15
14
13
12
11
12345678
91
0
*IC7308
OE1
A0
A1
A2
A3
A4
A5
A6
A7
GND
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
OE2
VCC
FE_CI1_INPACKB
*R7326
10k
*C7312
XX
*R7300
10k
20
19
18
17
16
15
14
13
12
11
12345678
91
0
*IC7305
OE1
A0
A1
A2
A3
A4
A5
A6
A7
GND
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
OE2
VCC
FE_CI1_CE1B
20
19
18
17
16
15
14
13
12
11
12345678
91
0
*IC7306
OE1
A0
A1
A2
A3
A4
A5
A6
A7
GND
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
OE2
VCC
*R7312
47
20
19
18
17
16
15
14
13
12
11
12345678
91
0
*IC7301
DIR
A0
A1
A2
A3
A4
A5
A6
A7
GND
B7
B6
B5
B4
B3
B2
B1
B0
OE
VCC
*C7310
0 . 1
*R7320
100
20
19
18
17
16
15
14
13
12
11
12345678
91
0
*IC7309
OE1
A0
A1
A2
A3
A4
A5
A6
A7
GND
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
OE2
VCC
*R7327
10k
*C7307
0 . 1
FE_CI_TSD[0-7]
*C7313
0 . 1
*C7300
0 . 1
*R7328
10k
47
*R7310
FE_CI1_WAITB
FE_FWEB
FE_RADD[0-11]
*FB7307
0uH
*FB7301
0uH
*R7325
10k
*R7303
10k
FE_IOWRB
*C7305
1000p
*R7324
10k
GND_1
FE_IOWRB_FWEB
FE_CI1_IREQB
*R7332 1k
*FB7303
0uH
*C7302
0 . 1
JL7300
*R7315
47
*C7308
0 . 1
*FB7304
0uH
FE_CI1_CD1B
GND_1
FE_NCI1_OVR
FE_CI1_RSTB
47
*R7311
*FB7305
0uH
*R7301
XX
FE_RDATA[0-7]
0uH
*FB7309
FE_NCI_EN
*R7331
1k
*R7306
220
FE_FOEB
8765
4
3
2
1
*IC7310
EN
FLAG
GND
NC
NC
OUT
IN
OUT
JL7301
FE_M_CKOUT,FE_M_SYNC,FE_M_VAL
*R7305
100
FE_BUF_DIR
GND_1
*R7329
10k
FE_IORDB
*R7317
47
*R7318
47
*R7309
10k
*R7316
47
54
3
2
1
*IC7300
A
B
GND
Y
VCC
20
19
18
17
16
15
14
13
12
11
12345678
91
0
*IC7304
OE1
A0
A1
A2
A3
A4
A5
A6
A7
GND
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
OE2
VCC
FE_FWEB
*FB7302
0uH
*C7301
0 . 1
FE_REGB
*R7314
47
FE_M_DATA[0-7]
*R7333 47
54
3
2
1
*IC7302
A
B
GND
Y
VCC
*C7314
4 . 7
FE_CI_TSD[7]
FE_CAM_TSIVAL
FE_CAM_TSOSYNC
FE_FOEB
FE_CAM_ADD[7]
FE_CAM_TSISYNC
FE_CI_TSD[1]
FE_RADD[8]
FE_CAM_ADD[5]
FE_RADD[1]
FE_CAM1_INPACKB
FE_CAM_TSIVAL
FE_CAM_TSOD[3]
FE_CAM_ADD[10]
FE_CAM_DAT[4]
FE_CAM_DAT[0]
FE_RDATA[1]
FE_CAM_OEB
FE_CAM_DAT[2]
FE_CAM_TSOD[5]
FE_D_IOWRB
FE_CAM_TSOD[0]
FE_CAM_OEB
FE_CI_TSSYNC
FE_RDATA[6]
FE_CAM_ADD[3]
FE_REGB
FE_CAM_ADD[8]
FE_CI1_WAITB
FE_RADD[9]
FE_CAM1_CE1B
FE_IORDB
FE_CAM_ADD[2]
FE_CAM_TSID[3]
FE_CAM_ADD[10]
FE_CAM1_RSTB
FE_CAM_TSID[0]
FE_CAM_DAT[0]
FE_CAM_IORDB
FE_RADD[11]
FE_IORDB
FE_CAM_DAT[7]
FE_CAM_TSID[6]
FE_CAM_TSOD[7]
FE_CI1_RSTB
FE_CI_TSD[5]
FE_CI1_CE1B
FE_CAM1_IREQB
FE_CI_TSD[2]
FE_CAM_WEB
FE_RADD[4]
FE_CAM_ADD[9]
FE_CAM_TSOD[3]
FE_CAM_TSID[5]
FE_CI_TSD[0]
FE_CAM_TSOSYNC
FE_CAM_ADD[7]
FE_CAM_TSID[5]
FE_CAM_TSOD[4]
FE_CAM_ADD[11]
FE_CAM_ADD[8]
FE_CAM_TSID[1]
FE_CAM_ADD[5]
FE_CAM1_RSTB
FE_CAM_TSID[6]
FE_CAM_TSID[2]
FE_FWEB
FE_RDATA[4]
FE_CAM_TSOD[4]
FE_CAM_REGB
FE_CAM_TSID[3]
FE_RDATA[5]
FE_CI_TSD[4]
FE_CAM_TSOD[5]
FE_CAM_TSOD[0]
FE_CI1_IREQB
FE_FWEB
FE_CI1_RSTB
FE_CAM_TSOVAL
FE_CAM_DAT[2]
FE_CAM_TSOVAL
FE_CI1_CE1B
FE_M_DATA[6]
FE_CAM_ADD[2]
FE_M_VAL
FE_D_IOWRB
FE_CAM1_WAITB
FE_CI_TSCLK
FE_CAM_DAT[5]
FE_CAM_TSOCLK
FE_RADD[0]
FE_CAM_DAT[1]
FE_CAM_DAT[3]
FE_M_DATA[5]
FE_CAM_ADD[1]
FE_RADD[2]
FE_CI_TSD[6]
FE_CAM_ADD[4]
FE_CAM_ADD[4]
FE_CAM_ADD[0]
FE_CAM_TSID[2]
FE_RADD[7]
FE_M_DATA[4]
FE_CAM1_WAITB
FE_CAM_TSISYNC
FE_RADD[5]
FE_CAM_TSID[4]
FE_CAM_TSOD[2]
FE_CAM_TSOCLK
FE_CAM_TSID[4]
FE_RDATA[3]
FE_CAM_ADD[0]
FE_CAM_ADD[3]
FE_CAM_DAT[6]
FE_CAM_TSICLK
FE_CAM_ADD[1]
FE_CAM_ADD[9]
FE_CAM_ADD[6]
FE_CAM_IOWRB
FE_RADD[3]
FE_CAM_TSID[7]
FE_CI_TSD[3]
FE_M_DATA[3]
FE_CAM_TSOD[1]
FE_REGB
FE_CAM_ADD[11]
FE_CAM_TSOD[2]
FE_CAM_IOWRB
FE_M_DATA[2]
FE_CAM_DAT[1]
FE_CAM_ADD[6]
FE_CAM_TSID[1]
FE_CI1_INPACKB
FE_M_SYNC
FE_M_DATA[1]
FE_CAM1_IREQB
FE_CAM_TSID[7]
FE_CAM_DAT[3]
FE_CAM_TSOD[7]
FE_M_DATA[0]
FE_CAM_DAT[4]
FE_CAM_TSICLK
FE_CAM_TSOD[1]
FE_RDATA[0]
FE_CAM_TSOD[6]
FE_CAM_DAT[7]
FE_CAM_DAT[5]
FE_CAM1_INPACKB
FE_RADD[10]
FE_M_DATA[7]
FE_CAM_DAT[6]
FE_CI1_INPACKB
FE_CAM_TSID[0]
FE_CAM1_CE1B
FE_RADD[6]
FE_RDATA[2]
FE_FOEB
FE_CAM_TSOD[6]
FE_CAM_REGB
FE_RDATA[7]
FE_CAM_WEB
FE_CI1_IREQB
FE_CI_TSVAL
FE_CAM_IORDB
FE_CI1_WAITB
FE_M_CKOUT
A l l J L ’ s a r e 0 . 6 m m u n l e s s o t h e r w i s e s t a t e d
EMMA2LR
EMMA2LR
EMMA2LR
EMMA2LR
A l l R ’ s & C ’ s a r e s i z e 1 0 0 5 u n l e s s o t h e r w i s e s t a t e d
EMMA2LR
DATA to/from CAM
EMMA2LR
5V SWITCH
ADDR to CAM
TS to CAM
TS to CAM
TS to EMMA
CTRL to/from CAM
EMMA2LR
TS from CAM
PCMCIA DVB-CI CONNECTOR
EMMA2LR
EMMA2LR
POWER
3.3V_MAIN
B2
3B/13
B2.-SE2
B2
3A/13
B2
3C/13
B2
3D/13
COMPONENTS MARKED AS XX REFER TO PARTS LIST, WILL ONLY BE LISTED IF FITTED
3.3V_MAIN
3.3V_MAIN
3.3V_MAIN
3.3V_MAIN
5V_MAIN
~ B2 Board Schematic Diagram [ Main Microcontroller, Scarts, AV Side & Component Input ] Page 3/13 ~
Ver 2.0
Click on the first or last page to see other KDL-20G3000 / KDL-20G3030 service manuals if exist.