Sony KDE-55XBR950 Service Manual ▷ View online
KDE55XBR950 (UC) 1-10
1-2-5. A BOARD REMOVAL
1
RF
cable
8
RF
cable
7
A board
2
Two screws
(+PSW 3x8)
2
Two screws
(+PSW 3x8)
3
D block assy
5
Case(UP)
M block shield
4
Two screw
(+PSW 3x8)
6
Three screws
(+PSW 3x8)
4
Two screw
(+PSW 3x8)
KDE55XBR950 (UC) 1-11E
1-2-6. M AND UD BOARDS REMOVAL
1
Four screws
(+PSW 3x8)
2
UD board
4
M board
3
Five screw
(+PSW 3x8)
KDE55XBR950 (UC) 2-1E
SECTION 2
ADJUSTMENTS
2-1.
White Balance Adjustment
2-1-1. Measuring instruments
1.
Color analyzer (Minolta CA-100)
2.
Signal oscillator VG-828D
2-1-2. Adjustment procedure
1.
Plug the AC cable into the panel unit, and check the fade-in
effect of the SONY LOGO LED.
effect of the SONY LOGO LED.
Checking SONY LOGO LED blinking
2.
Press the white balance adjustment jig CA-100 against the
panel grass surface.
panel grass surface.
3.
Connect the signal oscillator VG-828D to the DVI terminal.
4.
Input the magic square pattern of gradation level 211.
5.
Set the following items in the service mode menu.
TEST_MODE
: 1
POWER
: 1
SET_FEATURE
: 0
WHITE_BALANCE
: 0
PLEC
: 1
GAMMA
: 4
DITHER
: 0
CONTRAST
: 63
UPCS
: 1
CONTRAST_OFFSET : 45
BRIGHTNESS
: 31
UBCS
: 1
BRIGHTNESS_OFFSET : 31
R_GAIN_OFFSET
: 31
G_GAIN_OFFSET
: 31
B_GAIN_OFFSET
: 31
R_BIAS_OFFSET
: 31
G_BIAS_OFFSET
: 31
B_BIAS_OFFSET
: 31
SUBBRIGHT_R
: 1024
SUBBRIGHT_G
: 1024
SUBBRIGHT_B
: 1024
RKOF
: 0
GKOF
: 0
BKOF
: 0
PDRV_SUBCONT_R : 512
PDRV_SUBCONT_G : 512
PDRV_SUBCONT_B : 512
Check item
Defect of temperature sensor (Check
DEF board CN3306 and relay connector
for abnormality or disconnection.)
DEF board CN3306 and relay connector
for abnormality or disconnection.)
- Harness disconnection between DEF
board CN3801 and PANEL
- Harness disconnection between GF1/
GF2 boards and PANEL (PANEL side:
CN301, CN302, GF1/GF2 side:
connectors)
When no problem is found, there may
be defect in NPD module.
board CN3801 and PANEL
- Harness disconnection between GF1/
GF2 boards and PANEL (PANEL side:
CN301, CN302, GF1/GF2 side:
connectors)
When no problem is found, there may
be defect in NPD module.
GF1 board 3.3 V output
Harness disconnection between DEF
board CN3304 and GF1 board
Harness disconnection between DEF
board CN3304 and GF1 board
GF1 board “Low+B” output
Harness disconnection between DEF
board CN3304 and GF1 board
Harness disconnection between DEF
board CN3304 and GF1 board
Harness disconnection between DEF
board CN3301 and KF1 board
board CN3301 and KF1 board
Display
Repeat of red
blinking (4 times)
blinking (4 times)
Red/green blinking
Repeat of red
blinking (6 times)
(Approx. 6 seconds
from power ON)
blinking (6 times)
(Approx. 6 seconds
from power ON)
Repeat of red
blinking (6 times)
(Approx. 12 seconds
from power ON)
blinking (6 times)
(Approx. 12 seconds
from power ON)
Repeat of ewd
blinking (7 times)
blinking (7 times)
6.
Adjust “R_GAIN_OFFSET”, “G_GAIN_OFFSET”, and
“B_GAIN_OFFSET” in the service mode menu so that the
following specified values are satisfied.
Always adjust one of “R_GAIN”, “G_GAIN”, and
“B_GAIN” to 225, and adjust parameters for the others to
meet the following specified values.
“B_GAIN_OFFSET” in the service mode menu so that the
following specified values are satisfied.
Always adjust one of “R_GAIN”, “G_GAIN”, and
“B_GAIN” to 225, and adjust parameters for the others to
meet the following specified values.
7.
Save the adjustment values.
8.
Execute the following from the JIG PC with the UART
control.
control.
8-1. Set WHITE_BALANCE=1, and then carry out step 6.
8-2. Set WHITE_BALANCE=2, and then carry out step 6.
8-3. Set WHITE_BALANCE=3, and PLEC=0 and then
8-2. Set WHITE_BALANCE=2, and then carry out step 6.
8-3. Set WHITE_BALANCE=3, and PLEC=0 and then
carry out step 6.
9.
Input the following signals from the signal oscillator to check
brightness.
9-1. When all-white signal (195/255) is input
brightness.
9-1. When all-white signal (195/255) is input
Brightness Y=42 cd/m
2
or more
9-2. When 1/25Window signal (204/255) is input
Brightness Y=220 cd/m
2
or more
10. Detach the white balance adjustment jig CA-100 from the
grass surface.
W/B
X
Y
6500K+8MPCD
0
0.3133
± 0.003
0.3297
± 0.003
8000K+8MPCD
1
0.2944
± 0.003
0.3100
± 0.003
9300K+8MPCD
2
0.2838
± 0.003
0.2981
± 0.003
13550K
3
0.2684
± 0.003
0.2700
± 0.003
KDE55XBR950 (UC) 3-1
3-1. BLOCK DIAGRAMS
3-1-1. DISPLAY UNIT (PDM-5510)
SECTION 3
DIAGRAMS
CN3101
A1
A3
A4
B5
A6
B6
A7
B7
A8
B8
B9
A10
A11
B11
A13
B13
UART_I-
UART_I+
UART_O-
POWER ON
UART_O+
MODE
JIG
CABLE DET
SIRCS+
RXD
TXD
SIRCS-
SPDIF+
RESET
SPDIF-
STBY
TO
MEDIA
RECEIVER
UNIT
(BLACK)
CN3102
1
2
6
7
9
10
14
16
17
18
23
24
DATA2-
DATA2+
DDC SCL
DDC SDA
DATA1-
DATA1+
+5V POWER
HOTPLUG DET
DATA0-
DATA0+
CLOCK+
CLOCK-
(WHITE)
UNIT
RECEIVER
MEDIA
TO
D3108-D3111
OVER VOLTAGE
PROTECTER
2
+3.3V-4
7
8
5
6
5
6
7
8
2
3
2
3
8
11
3
5
RES
MODE
PXD1
TXD1
MODE
RXD1
TXD1
JIG
10
9
13
12
1
2
4
6
Q3110
IC3102
BUFFER
2
3
5
6
1
7
Q3118
SW
DET
1
IC3111,IC3103
LINE DRIVE
1
1
3
RXD0
SPDIF
SIRCS
TXD0
3.3V-4
PD1
PD0
4
1
D3104,D3106
LIMITER
Q3101
SHIFT
LEVEL
Q3105
+3.3V
+5V-4
8
BUS LINE BUFFER
IC3104
2
7
3
6
SCL
SDA
IC3101
VOLTAGE COMP.
IC3108
EEPROM
SDA
SCL
WP
13
3
5
6
7
Q3108
4
WP
9
10
SEL0
SEL1
6
SERIAL BUS SELECT
IC3107
12
14
15
11
1
5
2
4
Q3111
LEVEL
SHIFT
SDA
SCL
IC3109
TMDS RECEIVER
PROM SDA
DDC SDA
PROM SCL
DDC SCL
80
81
83
84
86
87
89
90
RX2+
RX2-
RX1+
RX1-
RX0+
RX0-
RXC+
RXC-
96
93
95
92
QE16
QE23
QE7
QE0
QE15
QE8
37
30
20
27
10
17
8
R0-R7
220
205-208
193-195
B0-B7
8
G0-G7
8
229
236-232
241
217-219
253,254
289
277,278
265,266
242
IC3110
48
182
157
HSYNC
VSYNC
DE
0DCK
47
46
44
181
171
197
GY10
GY17
BU10
BU17
RV17
RV10
HSCS1
HSADOUT1
VS1
DE1
CLK1
CPU
IC3501
RAO0
RAO9
BAO9
BAO0
GAO9
GAO0
HSO
VSO
DEO
OFPARITY
CLKO
40-42
44-46
62,63
6,8
1,9,11
64
52-54
48-50
10
G0-G9
10
B0-B9
4,5
33-38
59,61
R0-R9
10
178
162,166
154-156
129,130
103,104
204,215
216,222
226,228
237-240
168
179,180
190-192
201-203
214
399
426
427
454
373
55
57
58
3
12
13
TE0,TE1
TA0-TA5
TE4,TE5
TB6
TC0-TC3
TD0,TD1
TD2,TD3
TB0-TB4
TA6
TE2,TE3
TC4
TC5
TC6
TD6
CLKIN
PWDN
IC3801
LVDS TRANSMITTER
TA-
TA+
TB-
TB+
TC-
TC+
TCLK-
TCLK+
TD-
TD+
TE-
TE+
CN3801
3
4
5
6
7
8
10
11
12
13
14
15
19
21
23
25
27
29
TA-
TA+
TB-
TB+
TC-
TC+
TCLK-
TCLK+
TD-
TD+
TE-
TE+
SCL
SDA
CPUG0
PDPG0
IRQ
PDWN
SCL
SDA
CPUG0
PDPG0
IRQ
5
TO 2/2
DQ31
DQ00
A0-A11
BA0-BA1
DM0-DM3
MREF
WEN
CASN
RASN
CSN
DQS
CKE
CKN
CKP
SDRAM
DOUBLE DATA RATE
IC3602
DQ0
DQ31
A11
A0
BA1
BA0
DM0-DM3
VREF
WE
CAS
RAS
CS
DQS
CKE
CK
CK
1-7
9-15
28-41
57,59,60,64
32
72-75
47-50
22-25
45,47-51
31-34,36,37
12
2
4
29
30
19,45
20,21
46,71
23,24
56,57
115
67
18
44
43
8
42
16
17
58
25
26
27
28
94
53
54
55
TO
PDP
UNIT
31
30
29
28
25
24
23
22
21
20
19
18
DEF(1/2)
TMDS RECEIVER,
LVDS TRANSMITTER
Q3120
Q3119
TO 2/2
TO 2/2
TO 2/2
TO 2/2
TO 2/2
TO 2/2
TO 2/2
TO 2/2
TO 2/2
8
SCDT
SCDT
TO 2/2
7
TO 2/2
8
P_MUTE
Q3801,Q3802
IC3802
RESET
OUT
VCC
4
2
+3.3V
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