Sony KDE-42XBR950 / KDE-50XBR950 Service Manual ▷ View online
1-8 KDE42XBR950/KDE50XBR950 (UC)
1-3. CABLE ARRANGEMENTS FOR MEDIA RECEIVER UNIT(MBD-XBR950)
1-3-1. CN9401 LEAD ARRANGEMENT
ON A BOARD
Front side
Rear side
D block assy
(DIC)
(ATSC)
G board
A board
QH board
A board
HOLDER,WIRE
CN9401
⇓
1-3-2. i-LINK CABLE ARRANGEMENT
G board
Front side
Rear side
A board
D block assy
(DIC)
(ATSC)
CORE,FERRITE
CORD WITH
CONNECTOR(I-LINK)
CONNECTOR(I-LINK)
HOLDER,WIRE
1-3-3. FAN LEAD, RELAY CABLE, AND PIN
CABLE ARRANGEMENTS
Front side
Rear side
D block assy
(DIC)
(ATSC)
G board
A board
(ATSC)
G board
ANT-SW
HOLDER,WIRE
HOLDER,WIRE
CONNECTOR(DC,FAN)
DC,FAN
CABLE,PIN(MAIN)
CABLE,PIN(SUB)
CABLE,PIN(ATSC)
⇓
1-3-4. CABLE ARRANGEMENTS NEAR
ANTENNA SWITCH
Front side
Rear side
D block assy
(DIC)
(ATSC)
G board
A board
(ATSC)
ANT-SW
G board
HOLDER,WIRE
CORE,FERRITE(I-LINK)
CORE,FERRITE(A.C.)
⇓
KDE42XBR950/KDE50XBR950 (UC) 1-9E
1-3-5. CABLE ARRANGEMENTS NEAR D BLOCK
Front side
Rear side
D block assy
(DIC)
(ATSC)
G board
Direction A
A board
⇓
1-3-6. LVDS CABLE ARRANGEMENT
Front side
Rear side
G board
Direction A
Direction B
D block assy
(DIC)
(ATSC)
(Countermeasure against EMI)
⇓
TAPE,ELECTRIC
CONDUCTION
CONDUCTION
Fig.4
TAPE,ELECTRIC
CONDUCTION
CONDUCTION
Fig.3
TAPE,ELECTRIC
CONDUCTION
CONDUCTION
Fig.2
CONNECTOR(LVDS)
TAPE,ELECTRIC
CONDUCTION
CONDUCTION
Fig.1
To secure margin against EMI of around 400 MHz,
route the LVDS harness using the following
procedure:
procedure:
1. Route the LVDS connector upward from the exit of the
D block, and secure it on the side of the shield upper
cover of the D block with conductive tape.(Fig.1)
cover of the D block with conductive tape.(Fig.1)
2. Secure the tape (white) portion bundling the LVDS
harness to the corner of the DIC shield upper cover of the
D block with conductive tape, and bend the harness as
shown in Fig. 1.(Fig.2)
D block with conductive tape, and bend the harness as
shown in Fig. 1.(Fig.2)
3. Route the LVDS harness through the slot on the DIC and
ATSC and secure it with conductive tape.(Fig.2)
4. Secure the LVDS harness under the drop-safe part; as a
guide, attach tape on the side edge of the shield upper
cover.(Fig.3)
cover.(Fig.3)
5. Secure the LVDS harness upward near the shield clamper
of the D block with conductive tape; as a guide, attach
tape above the connector on the chassis of the D block.
(Fig.4)
tape above the connector on the chassis of the D block.
(Fig.4)
6. Route the LVDS harness through the clamper, and secure
it with conductive tape so that it is held on the top in the
clamper.(Fig.4)
clamper.(Fig.4)
Note :
1.Ensure that the LVDS harness has no slack in steps 1
1.Ensure that the LVDS harness has no slack in steps 1
through 6.
2.When attaching the drop-safe part, be careful not to
entangle it in the portions of LVDS harness described in
steps 3 and 4.
steps 3 and 4.
The drop-safe part needs to be removed before the
above procedure.
The size of each conductive tape should be 19 mm x 40
mm, which is the same size as 4-101-007-01 attached on
the exit of the LVDS connector.
the exit of the LVDS connector.
KDE42XBR950/KDE50XBR950 (UC) 2-1E
SECTION 2
ADJUSTMENTS
2-1. VS, VD Voltage Adjustment
(PDM-4210/5010)
(PDM-4210/5010)
• Preparation for adjustment
1. Slide the DIP switch (S3201) No. 8 of P board to on
position with no silkscreen mark r.
2. Connect a digital voltmeter to the following terminals of
G board.
VS voltage=G board TP1701 (VS)-TP1502 (GND)
VD voltage=G board TP1501 (VD)-TP1502 (GND)
VD voltage=G board TP1501 (VD)-TP1502 (GND)
3. Connect a AC cord in DISPLAY UNIT.
4. Perform the adjustment in 10 seconds after connecting
4. Perform the adjustment in 10 seconds after connecting
the cord.
• Procedure for adjustment
1. Slide the DIP switch (S3201) No. 7 of P board to on
position with no silkscreen mark r.
2. Confirm the lighting of SONY LOGO LED.
3. Adjust the VS voltage to the following voltage value.
3. Adjust the VS voltage to the following voltage value.
VS voltage of proper value for each model.
Ex.) VS proper value=185V thru 185.6V at 185V.
(Check the proper value with a seal on upper left of
panel unit. Refer to right Fig.)
Ex.) VS proper value=185V thru 185.6V at 185V.
(Check the proper value with a seal on upper left of
panel unit. Refer to right Fig.)
4. Adjust the VD voltage to the following voltage value.
VD voltage ±0.3V of proper value for each model.
Ex.) VD proper value=64.7V thru 65.3V at 65.0V.
(Check the proper value with a seal on upper left of
panel unit. Refer to right Fig.)
Ex.) VD proper value=64.7V thru 65.3V at 65.0V.
(Check the proper value with a seal on upper left of
panel unit. Refer to right Fig.)
5. Check a Fan rotation.
6. Slide the DIP Switch (S3201) No. 7 of P board to the off
6. Slide the DIP Switch (S3201) No. 7 of P board to the off
position with the silkscreen mark r.
7. Slide the DIP Switch (S3201) No. 8 of P board to the off
position with the silkscreen mark r.
8. Disconnect an AC cord of DISPLAY UNIT.
9. Reconnect the AC cord in one second.
10. Assure that “POWER ON/STANDBY” LEDs is
9. Reconnect the AC cord in one second.
10. Assure that “POWER ON/STANDBY” LEDs is
flashing amber.
2-2. White Balance Adjustment
(PDM-4210/5010)
(PDM-4210/5010)
• Measurement equipment
1. Color analyzer (CA-100 manufactured by MINOLTA)
1. Signal generator (ASTRO DESIGN VG-828D)
1. Signal generator (ASTRO DESIGN VG-828D)
• Measuring procedure
1. Dab the W/B adjustment jig (CA-100) at the glass face
of the panel.
2. Connect the Signal generator (VG-828D) to the DVI
terminal.
3. Input All-white signal and set the picture mode to
DYNAMIC.
4. Select”PNLCTRL” in the service mode menu and set “0
WBNO” at “0”
5. Select “SCNR” “SCNB” of “PDPWB” in the service
mode menu, and then adjust following W/B standardized
+6V
–0V
–0V
values of 6500K, 8000K, 9300K, 10000K and 13550K
to following values of X/Y.
to following values of X/Y.
6. After adjusting the values, at the values of the “SCNR”
or “SCNB” exceeding 128 (initialize value).
1) Reset a lager value of the “SCNR” or “SCNB” at 128.
2) Set the White Balances with the last of items and
“SCNG” to the X/Y values above.
1) Reset a lager value of the “SCNR” or “SCNB” at 128.
2) Set the White Balances with the last of items and
“SCNG” to the X/Y values above.
7. After the above step, when these item are nonqualified
following conditions, set the largest one at 128 and
readjust the White Balance with the last two item.
1) No one of “SCNR”, “SCNB” and “SCNG” exceeding
128.
2) Confirm the item value 128 at least one item.
readjust the White Balance with the last two item.
1) No one of “SCNR”, “SCNB” and “SCNG” exceeding
128.
2) Confirm the item value 128 at least one item.
8. As a result above, input the sequential number of value
to the “SCNR”, “SCNB” and “SCNG”.
9. Repeat the same step 5 thru 8 for the W/B 1 thru 4 after
setting the “0 WBNO” at each W/B number.
10.Input following signals from the Signal generator (VG-
828D).
1) All-white signal (255/255) input
Y (luminance)=45cd/m
1) All-white signal (255/255) input
Y (luminance)=45cd/m
2
or more
2) 1/25Window (255/255) input
Y (luminance)=45cd/m
Y (luminance)=45cd/m
2
or more
W/B standardized values:
6500K+8MPCD
8000K+8MPCD
9300K+8MPCD
10000K
13550K
W/B
0
1
2
3
4
X
0.3133
±0.003
0.2944
±0.003
0.2838
±0.003
0.2806
±0.003
0.2684
±0.003
Y
0.3297
±0.003
0.3100
±0.003
0.2981
±0.003
0.2883
±0.003
0.2700
±0.003
W/B
X
Y
KDE42XBR950/KDE50XBR950 (UC) 3-1
3-1. BLOCK DIAGRAMS
SECTION 3
DIAGRAMS
3-1-1. DISPLAY UNIT (PDM-4210/5010)
DDC
DDC
D3104,3106
(BLACK)
STBY
B11
A7
MODE
JIG
(WHITE)
+3.3V
+3.3V
D3108
D3111
3.2V
Q3119,3120
IC3109
R4
R7
G0
G7
B0
B7
B0
B7
RO0
7
GO0
7
RO0
7
RV10
RV17
GY17
GY17
BU10
BU17
IC 3103,3111
LVD RX/TX
Q3251
EVEL SHIFT
IC3252
FPGA
CONCNFIGURATION
PROM
IC3102
+3.3V
Q3118
IC3104
IC3107
Q3111
SDA
SCL
Q3102
WP
SEL0
SEL1
SERIAL BUS SELEG
Q3105
5V
3.3V
LC
LY
SX
SY
IC3101
Q3101
RES
VOLTAGE COMP.
DET
VCC SW
7
IC3112(1/2)
84
85
86
87
26
8
PD
SCDT
PD2
2
2
3
3
2
8
5
6
5
6
7
12
14
15
11
1
5
2
4
10
9
9
6
2
1,4,10,13
12
8
5
3
11
3A
2Y
1A
4A
Q3110
SW
3Y
2A
1Y
4Y
8
OVER VOLTAGE
PROTECTER
27
SCL
P3
P1
P0
123,124
126
129-133
SDA
19
HSI
21 VSI
DIN
CCLK
TDI
DONE
INIT
PROGRAM
TCK
TDO
39
37
32
72
68
69
2
34
D0
CLK
1
VCC
2
TRST
3
TDI
4
TDO
5
TMC
6
TCK
7
MODE
8
GND
CN3251
8P
TDO
CE
OE
CF
TCK
40
DIN
43
DCK
44
HS
41
VS
42
VS1
181
HSCS1
182
CLKI1
197
DE1
171
HSADOUT1
167
43
TMS
TDI
5
3
31
15
13
10
7
SCL
SDA
WC
220,205
205,208
193,194
242,289
253,254
265,266
277,278
241,229
232,230
219,217
R0
R7
3
134-141
G0
G7
B0
B7
R0
R7
G0
G7
58-56
50-46
67-62
60-59
83
80-74
IC3105
Q3108
WP
SEL0
SEL1
SERIAL BUS SELEG
12
14
15
11
1
5
2
4
10
9
WC
1
4
PD0
PD1
3
2
RXD/TXD/RES
BUFFER
B+
AO
BO
MODE
RES
IIC BUFFER
6
5
WP
SDA
SCL
Q3116,3117
18 GCK2
44
ODCK
DCK
7
IC3110
46
47
48
21
DEI
VSYNC
HSYNC
8
P2
4-7
10-13
IC3253
VSO
DEO
DCK
HSO
RA01
RA09
GA01
GA09
BA01
BA09
IC3501(1/2)
CPU
168
179,180
190-192
201,202
214
103,104
129,130
154-056
166,167
203
226-228
215,216
237-240
18
16
15
14
13
12
11
9
8
7
RF-
RE+
RE-
RD+
RD-
RCLK+
RCLK-
RC+
RC-
RB+
CN3801
TO
PDP UNIT
-
IC3801
LVDS TRANSMITTER
50
49
47
46
44
42
41
39
38
37
45
36
33
32
31
29
28
34
27
26
25
23
22
21
20
19
PS+
PS-
MSEL
RH+
RH-
RG+
RG-
RF+
29
ALARML
6
5
4
RB-
RA+
RA-
RA01
RA09
GA01
GA09
BA01
BA09
1
79,80
93-96
99,100
1-10
81,84
77,78
85-92
RF-
RE+
RE-
RD+
RD-
RCLK+
RCLK-
RC+
RC-
RB+
-
RH+
RH-
RG+
RG-
RF+
RB-
RA+
RA-
54
55
56
63
22
64
SCK
SD
DE
VSYNC
HSYNC
PD
426
399
427
52
77
SCK
SD
DE
VSYNC
HSYNC
9
IC3802
R0
RI-
RI+
1
2
7
(LVDS TRANSMITTER,FPGA,,CPU)
DEM (1/2)
22
PSS
10
LVDS TRANSMITTER
IC3108
EEPROM
LEVEL SHIFT
D3107
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