DOWNLOAD Sony KD-32DX100U Service Manual ↓ Size: 19.07 MB | Pages: 112 in PDF or view online for FREE

Model
KD-32DX100U
Pages
112
Size
19.07 MB
Type
PDF
Document
Service Manual
Brand
Device
TV
File
kd-32dx100u.pdf
Date

Sony KD-32DX100U Service Manual ▷ View online

- 53 -
~
B4 Board Schematic Diagram [ 100 Hz Board ] page 6/6 ~
~
F1 Boar
d Sc
hematic Dia
gram [ A
C
 Input ] ~
~
F3 Boar
d Sc
hematic Dia
gram [ P
o
wer Switc
h ] ~
~
H2 Board Schematic Diagram [ SIRCS ] ~
~
F Board Schematic Diagram [ Lightening/Fuse ] ~
1
     (1/6) To (3/6)      (4/6)      (5/6)
26
To (1/6)
15
     (2/6) To (2/6)      (3/6)      (5/6)
To (3/6)
46
To (3/6)
46
To (3/6)
36
To (3/6)
39
To (3/6)
39
To (1/6) (3/6) (4/6) (5/6)
1
To (3/6)
37
To (1/6)      (5/6)
17
To (1/6) (3/6) (5/6)
8
To (3/6)
38
To (3/6)
36
- 54 -
~
G Boar
d Schematic Dia
gram [ P
o
wer Suppl
y ] ~
AB
CD
E
F
G
HI
J
K
L
M
N
1
2
3
4
5
6
7
8
9
1
0
1
1
- 55 -
~ G Boar
d Semiconductor Location 
T
a
b
le ~
~ G Printed 
Wiring Boar
d Conductor side ~
E
D
OI
D
5
1
0
6
D2
-
E
R
O
T
SI
S
N
A
R
T
2
0
1
6
Q1
-
J
2
0
0
6
D3
-
A3
2
0
6
D3
-
H3
0
0
6
Q1
-
M3
0
1
6
Q1
-
J
3
0
0
6
D4
-
G0
3
0
6
D4
-
G5
0
0
6
Q2
-
B5
0
1
6
Q1
-
L
4
0
0
6
D4
-
G1
3
0
6
D2
-
D6
0
0
6
Q4
-
H
8
0
0
6
D3
-
G2
3
0
6
D2
-
D7
0
0
6
Q3
-
H
9
0
0
6
D4
-
E3
3
0
6
D2
-
E8
0
0
6
Q4
-
D
0
1
0
6
D4
-
E4
3
0
6
D2
-
E9
0
0
6
Q4
-
E
1
1
0
6
D3
-
E
CI
0
1
0
6
Q2
-
B
2
1
0
6
D3
-
E1
0
0
6
CI5
-
G4
1
0
6
Q2
-
J
3
1
0
6
D3
-
A1
0
1
6
Q1
-
L
Note :
P
o
rtions of the circuit contained within 
the mar
k
ed areas as sho
wn ha
v
e
 high 
v
oltages present.
 Use care to pre
v
ent 
electr
ic shoc
k dur
ing inspection or repair
.
An Isolation 
T
ransf
or
mer m
ust be used
dur
ing an
y Ser
vice w
o
rk
 to a
v
oid possib
le
shoc
k hazard due to liv
e chassis
. The 
chassis of this receiv
er is directly 
connected to the po
w
er line
.
~ F3 Printed 
Wiring Boar
d Conductor side ~
~ F1 Printed 
Wiring Boar
d Conductor side ~
~ H2 Printed 
Wiring Boar
d Conductor side ~
~ F Printed 
Wiring Boar
d Conductor side ~
AB
CD
E
F
G
HI
J
K
L
M
N
1
2
3
4
5
6
7
8
9
10
11
- 56 -
el
b
a
T
e
g
atl
o
V
CI
o
N
f
e
R
o
N
ni
P
)
V(
e
g
atl
o
V
0
0
1
8
CI
13
.
0
23
.
4
31
.
4
51
.
4
60
.
3
74
.
0
1
0
1
8
CI
13
.
0
23
.
4
34
.
4
54
.
4
60
.
3
74
.
0
2
0
1
8
CI
11
.
4
24
.
0
34
.
0
54
.
0
64
.
0
74
.
0
3
0
1
8
CI
15
.
2
21
.
2
37
.
1
56
.
1
60
.
1
71
.
1
f
e
R
)
s(
)
e(
)
g(
)
b(
)
d(
)
c(
f
e
R
)
s(
)
e(
)
g(
)
b(
)
d(
)
c(
f
e
R
)
s(
)
e(
)
g(
)
b(
)
d(
)
c(
f
e
R
)
s(
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e(
)
g(
)
b(
)
d(
)
c(
0
0
1
8
Q0
6.
06
.
30
1
1
8
Q4
.
21
.
30
8
2
1
8
Q4
.
35
.
19
.
81
0
8
8
Q0
4.
07
.
4
6
1
0
1
8
Q0
6.
03
.
43
1
1
8
Q3
.
02
.
09
.
82
3
1
8
Q0
0
4.
32
0
8
8
Q0
4.
02
.
3
7
2
0
1
8
Q0
3.
03
.
45
1
1
8
Q6
.
89
.
80
5
3
1
8
Q6
.
22
.
39
.
87
0
8
8
Q0
3.
60
3
0
1
8
Q0
.
40
9.
88
1
1
8
Q0
0
0.
56
3
1
8
Q5
.
28
.
10
8
1
8
8
Q0
0
0.
5
4
0
1
8
Q0
4.
01
.
39
1
1
8
Q7
.
04
.
10
7
3
1
8
Q8
.
15
.
29
.
82
2
8
8
Q5
.
59
.
40
5
0
1
8
Q0
4.
02
.
30
2
1
8
Q7
.
03
.
20
1
0
2
8
Q0
6.
09
.
33
2
8
8
Q9
.
85
.
80
6
0
1
8
Q0
3.
03
.
42
2
1
8
Q5
.
04
.
10
2
0
2
8
Q0
8.
04
.
35
0
8
8
Q0
5.
23
3
7
0
1
8
Q0
3.
02
.
43
2
1
8
Q5
.
04
.
10
3
0
2
8
Q4
.
19
.
00
6
0
8
8
Q0
2.
15
3
1
8
0
1
8
Q4
.
22
.
30
7
2
1
8
Q4
.
15
.
10
5
5
4
8
Q1
.
17
.
19
.
81
5
8
8
Q0
4.
55
.
1
8
TP4
10us/div
2.44 Vp-p (V)
TP1
10us/div
148 Vp-p (V)
TP2
10us/div
152 Vp-p (H)
TP4
10us/div
1.12 kVp-p (H)
TP5
10us/div
5.56 Vp-p (H)
TP6
10us/div
1.84 kVp-p (H)
TP7
10us/div
242 Vp-p (H)
TP8
5ms/div
2.12 Vp-p (H)
TP9
2ms/div
106.4 Vp-p (H)
TP10
10us/div
2.36 Vp-p (H)
TP3
~
D Boar
W
a
vef
orms ~
~
D Boar
d IC 
V
o
lta
g
e
 T
a
b
le ~
~
D Printed 
Wiring Boar
d Conductor side ~
~
D Boar
d Semiconductor 
V
o
ltag
T
a
b
le ~
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