Sony DCR-TRV900 Service Manual ▷ View online
6
1-3. Clock Signal Block Description
The sampling clock frequency systems of the DCR-TRV900 are classified into
the followings.
(1) For the camera system and external video input system: 13.5 MHz
→
The sampling clock frequency for the camera signal that is specified by
the DV format.
(2) For the signal compression system: 18.0 MHz
→
As the clock frequency for the Y-signal data and the C-signal data is 13.5
MHz, a higher clock frequency of 18.0 MHz is used to compress them
into a single data.
(3) i. LINK system: 98.3 MHz
→
The sampling clock frequency for the DV terminal is specified to be 98.3
MHz.
(4) For interfacing the record system: 8.37 MHz
→
Because the record circuit is located in a separate circuit board, and to
ensure the interfacing, this sampling frequency is used.
(5) For record system: 41.85 MHz
(6) For the playback signal processing system: 20.925 MHz
→
The frequency that is suited for processing the playback signal, is se-
lected.
(7) For VIDEO OUT: 27.0 MHz
→
The over-sampling frequency is used to improve the waveform character-
istics of the video LINE OUT signal.
7
Clock Signal Block Description Diagram
IR
VIDEO-IN
Line-in
Decoder
Decoder
H-PLL
LINE-13.5MHz
BBI
2.1Vmin
AFCK
CAM-13.5MHz
A/D
BIR DS
SPCK
2
1
27.0MHz
SYSCK
TG
Divide
-by-2
-by-2
2.7 Vmin
2.7 Vmin
VCK
CCD
13.5 MHz is not supplied
when using CG of 6.75 MHz.
when using CG of 6.75 MHz.
13.5 MHz is supplied
the caseof DEKA PYRA.
the caseof DEKA PYRA.
EVF LCD
panel
CG
External
features
3
4
5
3
VCK
Built-in PLL
×
4/3
×
2
TRCK0
2.7Vmin
TRCK1
1
2
3
VFD
SFD
UNLOCKD-REC
Divide-by
-[3
+
21/35]
(27.0MHz)
24.576MHz
256fs
approx. 24.576MHz
VIDEO-OUT
fsc of NTSC=3.53MHz
(In the PAL mode also)
2.7Vmin
DV terminal
LIP
Built-in PLL
×
4
24.576MHz
JC-18.0MHz
4
TFD
1.8Vmin
REC-8.37MHz
CRCK
Divide-by-4
Built-in PLL
×
31/10
TRX
REC-41.85 MHz
Divide-by-2
Divide-by-5
1.8Vmin
HPCK
PB-20.925MHzr
PB-41.85MHz
r
TUTS
(Not used)
BCK1
BCK0
2.7Vmin
64fsr
=3.072MHz (In case of 48 kHz)
=2.048MHz (In case of 32 kHz)
=3.072MHz (In case of 48 kHz)
=2.048MHz (In case of 32 kHz)
AUDIO-PLL
×
512fs
(In case of
48 kHz)
48 kHz)
×
768fs
(In case of
32 kHz)
32 kHz)
Divide-by-2
(In case of
48 kHz)
Divide-by-3
(In case of
32 kHz)
(In case of
48 kHz)
Divide-by-3
(In case of
32 kHz)
ADA
ABC
..
..
AUDIO-IN & OUT
1.8 Vmin. and 2.7 Vmin. shown in the illustration are the clock voltage.
The VFD (27.0 MHz) and LIP (98.304 MHz) are used only inside of each IC.
Clock of the four systems that are LINE - 13.5 MHz
r
, 256 fs
r
, PB - 8.37 MHz
r
and PB - 41.35 MHz
r
deviate by
±
several percents. Other clocks have the fixed frequency.
Same as C1 of
φ
2
Frame PLL of the digital system.
Frame pulse
(30/1.001 Hz in NTSC.
25 Hz in PAL)
(30/1.001 Hz in NTSC.
25 Hz in PAL)
Track pulse
(150/1.001 Hz in NTSC.
150 Hz in PAL)
(150/1.001 Hz in NTSC.
150 Hz in PAL)
FRR
T
, TRR
T
Mechanism
controller
DRUM
TRW
TRF
1.8Vmin
RECCK
1.8Vmin
PBCK
PB-PLL
(built-in)
13.5 MHz from TG
(98.304MHz)
8
1-4. Power Reset Description
The HI controller is backed up by the lithium battery. Various data (clock data and
others) are backed up by the backup battery. When the main power of the DCR-
TRV900 is turned off, the HI controller is reset by the reset IC. Then the HI
controller resets the mechanism controller and the camera controller. The mecha-
nism controller that is in charge of the system reset, performs the following resets.
1 VTR reset
2 LIP reset
3 ADA reset
4 EEP reset
2 LIP reset
3 ADA reset
4 EEP reset
The camera controller resets the entire camera system.
When these resets are completed, the mechanism deck and the camera block are
initialized. Then the DCR-TRV900 enters the standby state.
Power supplies in use
The following three power supply systems are used.
(1) 2 V system (Operating range 1.8 V to 2.2 V)
→
Used at 1.9 V
(2) 3 V system (Operating range 2.7 V to 3.3 V)
→
Used at 2.8 V
(3) 5 V system (Operating range 4.5 V to 5.5 V)
→
Used at 4.6 V
POWER ON
System reset
Reset IC
HI controller
E
E
P
E
P
R
E
S
E
E
S
E
T
A
D
A
D
A
R
E
S
E
E
S
E
T
L
I
P
R
E
S
E
E
S
E
T
V
T
R
R
E
S
E
E
S
E
T
Camera reset
Camera controller
Mechanism controller
9
4.6
2.8
2.8
4.6
2.8
2.8
4.6
2.8
2.8
4.6
2.8
2.8
4.6
2.8
2.8
2.8
1.9
1.9
2.8
1.9
1.9
2.8
1.9
1.9
2.8
1.9
1.9
2.8
2.8
1.9
1.9
4.6
4.6
2.8
2.8
2.8
4.6
2.8
2.8
2.8
1.9
2.8
2.8
2.8
4.6
2.8
4.6
2.8
4.6
2.8
12, -6.5
12, -6.5
2.8
2.8
12
-6.5
2.8
Birds
EEPR
OM
Lens Driver
IRIS
TG
GCAM
CCD
2.8
2.8
2.8
2.8
4.6
4.6
2.8
2.8
4.6
2.8
2.8
4.6
2.8
2.8
4.6
2.8
2.8
OSD
LCD DAC
EVF DAC
IR
BBI
EVF
LCD
SIRCS
CHIME
2.8
2.8
CAM DDON
LANC
VTRDDON
EVFDDON
LCDDDON
Chime Power Cont
System reset
BACK UP
EVER
LANC DC OUT
5.2V
5.2V
UNREG
Camera
reset
reset
Independent reset
is used
is used
VTR reset
LIP reset
ADA reset
EEP reset
Reset
IC
Battery
LCD driver
CAP DRV
DRM DRV
DRM PREDRV
TRF
TRW
TRX
TFD
SFD
VFD
DAC
LIP
MIC AMP
ABC
ADA
AOI
EEPROM
EEPROM
IC759
HONEY
JPFG
DRAM(16M)
DRAM(4M)
PC card I/F
20MHz CLK
Lithium battery
HI controller
Mechanism controller
Switching
power supply
for VTR block
power supply
for VTR block
DD converter
Switching
power supply
for camera block
power supply
for camera block
Camera controller
DS converter
Angular
velocity sensor
velocity sensor
Power Reset Description Diagram
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