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The HI controller is always monitoring the input signal from the keyboard, LANC,

SIRCS and chime, and issues the corresponding command to mechanism control-

ler, camera controller, OSD, LCD driver and others.  The HI controllers and the

DCR-TRV900 system start up in the following sequence.

1 When a battery is installed, the main power is always supplied to the HI

controller as long as the main power is turned on.  The DCR-TRV900 entire

system is reset by the HI controller.  The HI controller monitors the input

signals all the time.

2 When the POWER ON command is issued from the HI controller as acti-

vated by the key input or any other input signals, the power is supplied to the

mechanism controller, camera controller and digital still controller.

3 Then the respective ICs that are connected to each controller are reset and

start their operations.

…

When the mechanism controller receives the mode transition commands from the

HI controller, it issues the commands to control the I/F that uses the i.- LINK, to

control the tape format (TFD), to control the LINE OUT signal (A01) and to con-

trol I/F (ABC) the microphone input signal.  The respective ICs perform their

function in accordance with the commands.  Status of these ICs are fed back to the

HI controller through the input controller so that the HI controller monitors and

controls the operating mode at all times.

…

When the camera controller receives the mode transition commands from the HI

controller, it performs the following functions.

1 EEPROM (IC757) data reading and writing
2 Timing generator (IC204) control
3 VAP (IC302) control
4 FOCUS, ZOOM and ND filter control and motor control
5 Defects compensation and others

At the same time when the above controls are performed, status of each controller

is fed back to the HI controller through the camera controller.

The mechanism controller and the camera controller are connected in parallel

with respect to the HI controller.  Therefore, when any communication between

the mechanism controller and the camera controller is desired, a command needs

to be sent through the HI controller.  For example, to send a command from the

mechanism controller to the camera controller, it needs to be sent from the mecha-

nism controller to the HI controller first, then from the HI controller to the camera

controller.

…

When the digital still controller receives the mode transition commands from the

HI controller, it performs the following functions.

1 It controls the file name and the header information when writing the com-

pressed data into the PC card and others.

2 It controls the file name and the header information when reading the com-

pressed data from the PC card and others.

LANC

KEY

EEPROM

Bus

SFD

VFD

ABC

AOI

DAC

EEPROM

LIP

TFD

IC1602

IC1601

IC1200

IC1501

Birds

TG

GCAM

IB

OSD

IC1502

CHIME

IC1602

          IC7401

          IC2203

        FK-4880
(Control Switch Block)

DISP bus 60 or 50Hz

I/O sync bus   60Hz/50Hz

Camera bus  50/60Hz

VSP bus  150Hz

DRS bus  150Hz

IC2204

HI Controller

LCD driver

TRX

TRF

A/D (VAP)

EEPROM

IC1814

IC1900

IC300

IC204

IC203

IC302

IC301

IC760

IC1600

IC1501

IC2001

IC1402

IC2002

IC2404

BBI

EVF DAC

LCD DAC

IC5001, 5102,
    5502

IC2401 

Mechanism Controller

IC302

Camera Controller

IC751

Digital Still Controller

SIRCS

The sampling clock frequency systems of the DCR-TRV900 are classified into

the followings.

(1) For the camera system and external video input system: 13.5 MHz

→

The sampling clock frequency for the camera signal that is specified by

the DV format.

(2) For the signal compression system: 18.0 MHz

→

As the clock frequency for the Y-signal data and the C-signal data is 13.5

MHz, a higher clock frequency of 18.0 MHz is used to compress them

into a single data.

(3) i. LINK system: 98.3 MHz

→

The sampling clock frequency for the DV terminal is specified to be  98.3

MHz.

(4) For interfacing the record system: 8.37 MHz

→

Because the record circuit is located in a separate circuit board, and to

ensure the interfacing, this sampling frequency is used.

(5) For record system: 41.85 MHz

(6) For the playback signal processing system: 20.925 MHz

→

The frequency that is suited for processing the playback signal, is se-

lected.

(7) For VIDEO OUT: 27.0 MHz

→

The over-sampling frequency is used to improve the waveform character-

istics of the video LINE OUT signal.

IR

VIDEO-IN

Line-in
Decoder

H-PLL

LINE-13.5MHz

BBI

2.1Vmin

AFCK

CAM-13.5MHz

A/D

BIR DS 

SPCK

2

1

27.0MHz

SYSCK

TG

Divide
-by-2

2.7 Vmin

2.7 Vmin

VCK

CCD

13.5 MHz is not supplied 
when using CG of 6.75 MHz.

13.5 MHz is supplied
the caseof DEKA PYRA.

EVF LCD 

panel

CG

External 

features

3

4

5

3

VCK

Built-in PLL

×

 4/3

×

 2

TRCK0

2.7Vmin

TRCK1

1  

2

3

VFD

SFD

UNLOCKD-REC

Divide-by

-[3 

+

 21/35]

(27.0MHz)      

24.576MHz

 

256fs

 

approx. 24.576MHz

 

VIDEO-OUT     

fsc of NTSC=3.53MHz

(In the PAL mode also)

2.7Vmin

DV terminal

 LIP

Built-in PLL

×

 4

24.576MHz

JC-18.0MHz

4

TFD

1.8Vmin

REC-8.37MHz

CRCK

Divide-by-4

Built-in PLL

×

 31/10

TRX   

REC-41.85 MHz

 Divide-by-2

 Divide-by-5

1.8Vmin

HPCK

PB-20.925MHzr

PB-41.85MHz

r

TUTS

(Not used)

BCK1

BCK0

2.7Vmin

64fsr
=3.072MHz (In case of 48 kHz)
=2.048MHz (In case of 32 kHz)

AUDIO-PLL

×

 512fs

(In case of
48 kHz)

×

 768fs

(In case of
32 kHz)

Divide-by-2
(In case of
48 kHz)
Divide-by-3
(In case of
32 kHz)

ADA

ABC

.. 

..   

AUDIO-IN & OUT     

1.8 Vmin. and 2.7 Vmin. shown in the illustration are the clock voltage.

The VFD (27.0 MHz) and LIP (98.304 MHz) are used only inside of each IC.

Clock of the four systems that are LINE - 13.5 MHz

r

, 256 fs

r

, PB - 8.37 MHz

r

 and PB - 41.35 MHz

r

deviate by 

±

 several percents.  Other clocks have the fixed frequency.

Same as C1 of 

φ

2

Frame PLL of the digital system.

Frame pulse
(30/1.001 Hz in NTSC.
25 Hz in PAL)

Track pulse
(150/1.001 Hz in NTSC.
150 Hz in PAL)

FRR

T

, TRR

T

Mechanism

controller

DRUM  

TRW

TRF

1.8Vmin

RECCK

1.8Vmin

PBCK

PB-PLL

(built-in)

13.5 MHz from TG

(98.304MHz)