Sony DCR-IP1 / DCR-IP1E Service Manual ▷ View online
DCR-IP1/IP1E
:Voltage measurment of the CSP ICs
and the Transistors with mark,are
not possible.
and the Transistors with mark,are
not possible.
D_2.8V
0
R1431
IC_1402_RST
SPCK
22u
4V
C1426
8200
±
0.5%
R1418
0.1u
C1416
0
R1407
±
0.5%
220k
R1421
±
0.5%
180k
R1426
XX
C1407
0
R1433
XX
C1428
0.001u
C1417
10uH
L1402
CAM_CS
±
0.5%
3300
R1427
C1410
XX
0.001u
C1420
±
0.5%
220k
R1428
CAM_SCK
A_2.8V
39k
±
0.5%
R1416
CAM_SO
±
0.5%
6800
R1417
0.01u
C1419
MT_5V
0
R1425
33u
10V
10V
C1405
DIR1B
2700
±
0.5%
R1411
C1427
XX
0.1u
C1403
2200p
C1413
0.1u
C1425
39k
±
0.5%
R1410
0.1u
C1421
CAM_VD
±
0.5%
180k
R1423
±
0.5%
3300
R1420
±
0.5%
4700
R1422
0.1u
C1414
0.1u
C1423
10uH
L1404
±
0.5%
6800
R1415
DIR1A
FB1401
0.1u
C1415
±
0.5%
10k
R1429
0
R1432
REG_GND
2200p
C1409
±
0.5%
10k
R1419
0
R1406
0.1u
C1404
0.1u
C1424
2700
±
0.5%
R1403
F_MR_A
F_MR_B
CXD9681GL-E2
IC1402
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
10k
R1424
8200
±
0.5%
R1430
M50237WG-DF0T
IC1401
D4
A1
B1
C2
C1
D3
D2
D1
E1
E3
E2
F1
F2
G1
G2
F3
E4
H1
H2
G3
H3
G4
F4
H4
H5
G5
F5
H6
G6
H7
G7
F6
E5
H8
G8
F7
F8
E6
E7
E8
D8
D7
D6
C8
C7
B8
B7
C6
D5 A8 A7 B6 A6 C5 B5 A5 A4 C4 B4 A3 B3 A2 B2 C3
I_BIAS-
FOCUS-
ND_DRIVE-
I_BIAS+
ND_BIAS+
FOCUS+
I_DRIVE+
ND_BIAS-
ZM_RST_SENS
ND_DRIVE+
I_DRIVE-
22u
4V
C1422
10uH
L1403
22u
4V
4V
C1402
0.1u
C1401
F_MR_A2.8V
ZOOM_XA
ZOOM_A
ZOOM_XB
ZOOM_B
EN01
UNRL11500AS0
Q1401
1
4
3
2
ZM_VCC
68k
R1401
ZM_RST_LED
ZM_RST_SENS
SHUTTER_DIR_PWM
SHUTTER_DRV_ON
SHUTTER_+
SHUTTER_-
A_4.6V
C1429
XX
XX
IC1403
1
2
3
4
5
XX
C1430
0.1u
C1418
1
A
I_HALL+
ND_HALL+
I_HALL-
ND_HALL-
CAM_SI
CAM_SCK
CAM_CS
IC_1402_RST
I_BIAS-
ND_BIAS+
ND_HALL_AD1
XIC_1402_RST
DIR1B
I_BIAS+
FOCUS+
ND_HALL-
FOCUS+
I_HALL-
ND_HALL+
F_MR_A
ND_DRIVE-
CAM_SO
CAM_SI
FOCUS-
I_HALL+
I_DRIVE-
I_DRIVE+
DIR1A
ND_BIAS-
ND_DRIVE+
ZOOM_B
F_MR_B
CAM_SCK
CAM_CS
CAM_SO
XIC_1402_RST
AD_FC_MR_A
AD_FC_MR_B
ND_BIAS-
ND_HALL-
ND_HALL_AD1
I_HALL_AD1
I_HALL+
CAM_SI
FC_EN
FC_PWM
IR_EN
IR_PWM
ND_EN
ND_PWM
I_HALL_AD1
F_MR_A
F_MR_B
I_HALL-
I_BIAS-
I_BIAS+
ND_BIAS+
ND_HALL+
AD_FC_MR_B
FC_PWM
FC_EN
I_DRIVE+
I_DRIVE-
ND_DRIVE-
ND_DRIVE+
IR_PWM
FOCUS-
ND_PWM
ND_EN
IR_EN
ZOOM_XB
ZOOM_B
AD_FC_MR_A
ZOOM_XA
ZOOM_A
ZOOM_A
ZOOM_XA
DIR1B
DIR1A
EN01
EN01
SHUTTER_DIR_PWM
SHUTTER_DRV_ON
SHUTTER_DRV_ON
SHUTTER_DIR_PWM
SHUTTER_+
SHUTTER_-
SHUTTER_+
SHUTTER_-
ZOOM_XB
OPIN4N
XCLR
AD_ZM_MR_B
OPIN0N
ZM_MR_A
OPOUT2
SO
VREF1
ND_BIAS+
FC_MR_A
IR7
OPOUT6
ZM_MR_B
CREFIN
AD_FC_MR_B
ND_BIAS-
OPOUT3
SCK
CS
DAC6OUT
OPOUT1
AVSS
DAC3OUT
I_RHALL+
OPOUT0
ND_HALL-
AD_FC_MR_A
AD_ND
IR_EN
SI
ND_EN
DVSS
OPOUT4
AVDD
DAC2OUT
ND_PWM
IR5
VD
OPIN3N
ZM_PWM
I_RHALL-
AD_ZM_MR_A
FC_MR_B
OPIN2N
DAC1OUT
FC_PWM
OPIN1N
TEST1
ND_HALL+
I_RBIAS-
OPIN6N
IR_PWM
FC_EN
DAC4OUT
TEST3
CLK
VREF2
TEST2
DAC0OUT
DVDD
ZM_EN
I_RBIAS+
TEST0
AD_IR
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
EN5
NC
VREF
VLIM
IN6
EN7
IN7
BR6
NC
EN1
EN3
PS
IN2
NC
EN2
NC
BR5
IN1
NC
NC
NC
RNFS
IN3
EN4
IN4
NC
NC
NC
IN5
EN6
PGND3
OUT5A
VM3
OUT5B
PGND3
OUT6A
PGND3
OUT6B
VM3
PGND1
VM1
OUT1A
OUT1B
OUT2B
OUT2A
VM1
PGND1
PGND1
DGND
OUT7A
VM4
VM4
RNF
OUT7B
OUT4B
PGND2
VM2
OUT4A
OUT3A
VM2
PGND2
OUT3B
PGND2
VCC
Vo
Vi
Vref
GND
CE
B+ SWITCH
E
H
9
8
13
18
4
K
B
3
2
G
05
17
J
12
7
15
F
5
6
LENS DRIVE
11
VC-333 BOARD (4/18)
I
XX MARK:NO MOUNT
D
16
C
14
10
IC1401
IC1402
FOCUS MOTOR CONTROL,
ND FILTER CONTROL,
IRIS CONTROL
FOCUS/ZOOM
MOTOR DRIVE,
ND FILTER DRIVE,
IRIS DRIVE,
LENS COVER
MOTOR DRIVE
(1/18)
1
(17/18)
91
(12/18)
92
42
(3/18)
(12/18)
93
94
(12/18)
(18/18)
95
(2/18)
27
89
(3/18)
97
(12/18)
40
(3/18)
(12/18)
98
4-17
4-18
VC-333 (4/18)
4-2. SCHEMATIC DIAGRAMS
VC-333 BOARD SIDE A
VC-333 BOARD SIDE B
4-2. SCHEMATIC DIAGRAMS
VC-333 BOARD SIDE A
VC-333 BOARD SIDE B
For Schematic Diagram
• Refer to page 4-67 for printed wiring board.
• Refer to page 4-67 for printed wiring board.
DCR-IP1/IP1E
:Voltage measurment of the CSP ICs
and the Transistors with mark,are
not possible.
and the Transistors with mark,are
not possible.
SFD_LRCK
HADR[9]
ED2
HADR[11]
ED3
10k
R709
FB706
FB701
10k
R706
HADR[6]
R716
10k
C706
4.7u
4.7u
DSCK_LK
WE1_LK
10k
R707
ED6
ED0
BCK
RCO2_EDFLD
R719
10k
HADR[10]
ED7
HADR[8]
HADR[3]
C701
4.7u
ED1
FB705
WROX
FB703
10k
R708
HDAT[0]
RCO0_EDHD
D_1.2V
R718
10k
RD_LK
ADDE
10k
R703
HADR[4]
ED5
C705
4.7u
RYO2_DEFLD
HADR[0]
BSRE
RYO0_DEHD
ADECD
HADR[1]
C703
4.7u
10k
R704
HADR[5]
10k
R710
ABCK
REG_GND
MPLCK27
RYO1_DEVD
C711
4.7u
4.7u
HADR[2]
VCER
R717
10k
10k
R713
D_1.5V
D_2.8V
ED4
RCO1_EDVD
ADATAIN0
C712
4.7u
HADR[7]
R714
10k
HDAT[1]
IC_701_XRDY
10k
R705
10k
R711
RDX
C714 0.01u
C715 0.01u
C716 0.01u
C720
0.01u
C721
0.01u
C717
0.01u
C713
0.01u
C719
0.01u
C710
0.01u
CL701
INT_IC_701
XCS_IC_701
HDAT[2]
HDAT[3]
HDAT[4]
HDAT[5]
HDAT[6]
HDAT[7]
HADR[13]
HADR[12]
XRST_RFML
0
R720
R723
0
R715
XX
R722
0
SFD_BCK
0
R721
C724
XX
C709
0.01u
C722
0.01u
C707
0.01u
0.01u
C708
0.01u
C723
0.01u
0.01u
C702
4.7u
FB702
FB704
C704
4.7u
C718 0.01u
0
R712
FB708
XX
FB709
CXD3183GA-T6
IC701
DREQ_MUX
DREQ0_DMX
XCS_IC_701_L
A3_LK
A2_LK
D15_LK
A1_LK
D14_LK
D13_LK
D12_LK
D9_LK
D10_LK
D11_LK
D8_LK
D5_LK
D6_LK
D7_LK
D0_LK
D4_LK
D3_LK
D1_LK
D2_LK
R701
0
0
R724
1
A
AENCD
AEDE
ADATAOUT0
BS[2]
BS[7]
BS[3]
BS[1]
BS[5]
BS[4]
BS[6]
BS[0]
BSRDY
RYI0_DE0
RCI0_DE4
RCI1_DE5
RYI1_DE1
RYI2_DE2
RYI3_DE3
RCI2_DE6
RCI3_DE7
SDCK
SDADR9
SDDMSK
SDADR0
SDADR1
SDADR2
SDADR5
SDADR6
SDADR4
SDADR3
SDADR8
SDADR9
SDADR7
SDADR10
SDBA1
SDBA0
SDWE
SDRAS
SDCS
SDCAS
SDADR8
SDADR5
SDADR3
SDADR2
SDADR7
SDADR4
SDCK
SDADR10
SDADR1
SDWE
SDADR6
SDCS
SDBA1
SDADR0
SDCAS
SDDMSK
SDRAS
SDBA0
VIDEO1IF2
SDADR9
VS2IF(sync)
VIDEO2IF1
BS2IF1
SDDT1
TRST
TESTCLK
BS1IF5
SDDT23
GND1T_6
GND1T_2
SDADR10
HADR0
VCCIN_1
TDO2
TMODE2
BS1IF6
SDDT22
SDADR11
HADR4
VIDEO1IF4
SDDT4
BS2IF9
TDO
SDDT21
XRST
VCC3_2
VCC1T_1
BS1IF7
HADR5
BS2IF12
VIDEO1IF3
VCC2_1
BSRDREQ2IF
SDDT20
EXHCKS
HADR1
PWM
HDAT6
BSER1IF
RAM_VDD
GND3_6
HADR2
SDDT24
TESTCLKS
VCCIN_2
AENCD
HDAT7
BSRDY1IF
VCC3_6
RAM_VSS
SDCS
HADR3
GND1T_1
SDDT25
TMS
VCC3_7
GNDIN_1
VCC1_2
RAM_TPBI
BSADR2IF2
HADR6
VCC1T_2
CLKOUT
DVSPLL2
HDAT10
VCC2_3
SDCK
BSWE2IF
BSRE1IF
HDAT0
HADR7
SDDT26
HDAT5
SDADR0
CLKRST
SCK
HDAT9
HADR8
BCK1IF
SDADR5
BSEND2IF
SDADR1
SDDT18
TCK
DVDPLL2
HDAT8
HADR9
SDADR4
GND1_1
GND3_5
VCC1T_3
GNDIN_2
HADR10
BSADR2IF0
GND2_2
GND1T_5
HCS
RAM_VSSQ
BSWDREQ2IF
VIDEO1IF0
SDDT17
TMODE0
HADR11
VCK2IF
BCK2IF
VIDEO1IF1
BS2IF11
VCCIN_6
VCC2_5
HADR12
VCC2_4
RAM_VDD
BS2IF10
JBKIO1
SDDT14
VIDEO1IF5
SDDT3
HDAT1
GNDIN_4
SDDT27
VCC1T_7
AUCKFS
RAM_DQM00-3
BSRE2IF
SDDT7
SDDT11
VIDEO1IF6
RAM_VDD
BS2IF15
SDDT28
SDDT30
AUCK64FS
GND1_2
VCC1T_4
HRDY
GNDIN_9
VCCIN_4
VIDEO2IF15
SDDT29
VIDEO1IF7
BS2IF7
SDDT31
GNDIN_5
BS1IF3
VCC2_6
HIRQ
SDDT12
SDWE
VCC3_4
BS2IF8
RAM_TSTE
VCCIN_3
HDAT11
BS1IF1
VIDEO1IF8
SDDT8
SDDT13
GNDIN_7
HS2IF(sync)
SDDMSK
VCC3_3
BS1IF2
RAM_A6
SDDT10
RAM_A5
SDRAS
VIDEO1IF9
GNDIN_3
HRD
BS2IF5
BS1IF0
HDAT12
SDDT9
VCC1_1
HDAT4
BS2IF6
VIDEO2IF5
HDAT14
SDDT19
HDAT13
VIDEO2IF7
BS2IF13
VIDEO1IF10
HDAT2
VCC3_1
ARECD
VCCIN_9
VIDEO2IF2
VCC1T_5
VIDEO2IF8
BS2IF3
VIDEO1IF11
HDAT15
APBD
GND3_4
VIDEO2IF3
BS2IF4
VIDEO2IF9
VCCIN_7
HS1IF(sync)
GND2_6
ADECD
VIDEO1IF12
SDADR2
VIDEO2IF4
BS2IF14
VIDEO2IF10
VS1IF(sync)
HWRL
GNDIN_8
SDBA1
SDADR3
VCC3_5
SDADR7
VIDEO1IF13
VIDEO2IF11
VIDEO2IF6
VCK1IF
HWRH
GND1T_4
SDBA0
SDADR6
VCC2_2
ADDE
BSCS2IF
VIDEO1IF14
VIDEO2IF12
FID1IF(sync)
SDDT0
SDCAS
HDAT3
SDADR8
AEDE
SDADR12
SDDT15
VIDEO2IF13
HADR13
SDDT2
VIDEO1IF15
VCCIN_8
QBCK
RAM_A8
VIDEO2IF14
BS2IF0
EXHCK
VCCIN_5
SDDT6
BSADR2IF1
VIDEO2IF0
SDADR13
SDDT16
FID2IF(sync)
TDI
BS2IF2
SDDT5
TMODE1
BS1IF4
RAM_VDDQ
RAM_VSS
RAM_VSS
RAM_A9
RAM_A7
RAM_A4
RAM_A3
RAM_VDD
RAM_BA1
RAM_CS
RAM_VSS
RAM_VDDQ
RAM_A10
RAM_A0
RAM_VDD
RAM_CLK
RAM_A1
RAM_VDD
RAM_VDD
RAM_VSS
RAM_WE
RAM_A2
RAM_VSSQ
RAM_BA0
RAM_VDD
RAM_VDD
RAM_CAS
RAM_RAS
RAM_VSS
RAM_VSSQ
RAM_VSSQ
RAM_VSSQ
RAM_VDDQ
RAM_VDDQ
RAM_VDDQ
RAM_VDDQ
IC701
SDRAM
MPEG VIDEO/AUDIO CODEC,
VC-333 BOARD (5/18)
F
N
J
B
10
D
5
M
12
XX MARK:NO MOUNT
3
16
18
6
L
9
7
05
2
E
MPEG VIDEO/AUDIO CODEC
C
4
11
8
15
17
G
H
K
14
I
13
O
P
Q
VIDEO SIGNAL
Y/CHROMA
Y
PB
REC
SIGNAL
SIGNAL PATH
CHROMA
AUDIO
(12/18)
99
(3/18)
78
(10/18)
101
(10/18)
102
85
(3/18)
103
(6/18)
52
(3/18)
63
(3/18)
(3/18)
61
(12/18)
104
(3/18)
70
106
(6/18)
69
(3/18)
(3/18)
45
(3/18)
44
(12/18)
107
(12/18)
108
110
(12/18)
109
(12/18)
(18/18)
100
AD5
M2
AA6
AC6
Y6
AD6
N2
AD7
Y7
AA8
Y8
AC9
AD8
AA9
AD9
AC10
AD10
Y9
Y10
Y11
AD11
AA11
AD12
AA12
P4
R2
AA4
AA7
Y12
AD14
Y13
Y14
Y15
Y16
AD15
AC15
AD16
AA15
AD17
AC16
AD18
AA16
Y17
AA17
AC18
Y18
AD19
AC19
AD20
AA18
AD21
AC20
AA19
Y19
AD22
AC22
AC21
AA21
AB23
Y20
AB24
AA23
AA24
Y21
AC7
Y23
W20
W
23
Y24
W21
V20
W24
V23
V24
U23
V21
U24
U20
U21
T20
T24
T21
R24
R23
R20
R21
P24
P20
P21
N20
N24
N21
M24
M20
M23
L20
L24
AC8
L23
L21
K24
K20
J24
K21
J20
J23
H24
H20
G24
H21
G20
G23
F24
G21
F20
F21
E24
E23
D24
E20
D23
C23
C24
B22
AA10
B21
E19
D20
A22
B20
A21
D19
A20
B19
E18
D18
A19
E14
A18
B17
AC11
E17
D17
A17
E16
A16
B16
E15
A15
D15
AC12
B14
AA13
D14
A14
D13
A13
E13
A12
E12
E11
B11
A11
D11
E10
D10
A10
E9
A9
B9
A8
D9
E8
E7
A7
D8
A6
E6
AC13
B6
A5
D7
D6
E5
A4
D4
A3
B4
D5
AD13
AC14
AA14
AC17
AA20
T23
P23
N23
M21
K23
J21
H23
F23
E21
D21
B18
D16
B15
B13
B12
D12
B10
B8
B7
B5
K6
N6
V6
W6
W9
W15
F15
B3 C1 C2 G4 D2 D1 E4 E2 F5 E1 F2 F1 F4 G2 G5 G1 H5 H4 J5 H1 J2 J1 J4 K2 K4 K1 L2 K5 L4 L1 L5 M1 M5 N1 M4 N5
U2 U4 V2 Y1 V5 W2 V4 AA1 Y2 AB1 W5 AA2 W4 AC3 AB2 Y5 AD3 AC4 AD4 Y4
T5
W1
R1
V1
H2
U5
R5
T2
P2
U1
P5
T4
P1
T1
N4
R4
AA5 AC5
4-19
4-20
VC-333 (5/18)
For Schematic Diagram
• Refer to page 4-67 for printed wiring board.
• Refer to page 4-67 for printed wiring board.
4-2. SCHEMATIC DIAGRAMS
VC-333 BOARD SIDE A
VC-333 BOARD SIDE B
4-2. SCHEMATIC DIAGRAMS
VC-333 BOARD SIDE A
VC-333 BOARD SIDE B
DCR-IP1/IP1E
:Voltage measurment of the CSP ICs
and the Transistors with mark,are
not possible.
and the Transistors with mark,are
not possible.
8
2.8 Vp-p
10 msec (100 Hz)
JL801, JL802 (IC801
<
,
<
) REC/PB
F14
F17
0.1u
C820
REG_GND
D_2.8V
10u
6.3V
C819
4.7u
C822
4.7u
C821
D_1.5V
10uH
L803
FB801
RECA2
CTRL1
0.1u
C816
BSRE
BCK
VCER
BSRDY
QTM1
QTM2
RECCLK
0.1u
C813
PB_DATA
10uH
L801
0.1u
C815
4.7u
C818
10uH
L802
0.068u
C811
RECDT
0.1u
C812
XRST_RFML
100k
R807
MIC_SO
MIC_SCK
XCS_MIC
0.1u
C808
MIC_SI_EN
MIC_SI
BSD_OUT
BSD_IN
XREC_ACT_M
XREC_ACT_P
HDAT[0]
HDAT[1]
0.1u
C809
HDAT[2]
HDAT[6]
HDAT[3]
HDAT[4]
HDAT[5]
WROX
HDAT[7]
RDX
XCS_IC_801
SWP
RCO2_EDFLD
ENC_XDEC
REFSWP
HYI_PLL27IN
0.1u
C805
IC_601DIR
MFLG_QRST
FRATREFI_TFP
IC_601DEN
0.1u
C801
IC_601DT[0]
IC_601DT[6]
IC_601DT[3]
IC_601DT[5]
IC_601DT[4]
IC_601DT[1]
IC_601DT[7]
IC_601DT[2]
0.1u
C802
0.1u
C803
ABCK
ADECD
ADDE
AENCD
AEDE
0.1u
C806
0.1u
C807
XSRST_IC_801
HADR[0]
HADR[1]
HADR[2]
HADR[3]
HADR[4]
HADR[5]
HADR[6]
HADR[7]
HADR[8]
HADR[9]
HADR[10]
HADR[11]
RCO3_FRMREF
MPLCK27
DSCK_LK
IC_601ACC
0
R802
0
R803
0
R804
0
R809
A_2.8V
0.1u
C814
0.1u
C810
0.1u
C804
4.7u
C817
100k
R806
100k
R808
JL803
JL804
JL805
JL806
JL809
JL808
JL807
JL815
JL813
JL814
JL818
JL817
JL816
JL810
JL812
JL811
JL824
JL823
JL822
JL821
JL820
JL819
JL802
JL801
±
0.5%
XX
R811
±
0.5%
XX
R810
0
R812
CXD3177GL-T6
IC801
B2 C4 C3 B1 D4 D3 C2 C1 E4 E3 D1 D2 F4 F3 E1 E2 G4 F1 G3 F2 G1 H4 H3 G2 J4 H1 J3 H2 J1 K4 J2 K1 U1 K3 L1 K2
T2
R3
U2
P3
T3
U3
P4
R4
T4
P5
R5
U4
T5
U5
P6
R6
T6
U6
P7
R7
T7
U7
P8
R8
T8
U8
U9
P9
R9
T9
U10
P10
T11
T10
R10
U12
P11
R11
P12
U11
R12
U14
P13
R13
T12
U15
T13
P14
U16
T14
R14
T15
T16
P15
R15
T17
N14
R16
R17
N15
P17
P16
M14
M15
N17
N16
L14
M17
M16
L15
K14
L17
L16
K15
K17
J14
K16
J17
J15
H14
J16
H17
H15
H16
G17
G14
G15
G16
F17
F14
E17
F16
M3
R2
M2
T1
N1
P2
M4
R1
M1
N3
L2
P1
L3
N2
L4
N4
F15
D17
E16
E14
E15
C17
D16
D14
B17
C16
D15
B16
C15
A16
U13
B15
A15
C14
D13
A14
B14
C13
D12
A13
U17
B13
C12
A12
D11
B12
A11
C11
D10
B11
A10
C10
D9
B10
A9
C9
D8
A8
B9
C8
A7
B8
D7
A6
B7
C7
B6
D6
A5
C6
B5
A4
D5
C5
A3
B4
A2
B3
A17
A1
1
A
BS[7]
BS[0]
BS[5]
BS[1]
BS[6]
BS[3]
BS[4]
BS[2]
HADR[7]
HADR[3]
HADR[6]
HADR[8]
HADR[1]
HADR[2]
HADR[5]
HADR[0]
HADR[10]
HADR[11]
HADR[9]
HADR[4]
HYI_PLL27IN
XSRST_IC_801
ENC_XDEC
SWP
REFSWP
RCO2_EDFLD
XCS_IC_801
RDX
WROX
HDAT[7]
HDAT[6]
HDAT[5]
HDAT[4]
HDAT[3]
HDAT[2]
HDAT[1]
HDAT[0]
XREC_ACT_M
XREC_ACT_P
BSD_IN
BSD_OUT
MIC_SI_EN
MIC_SI
MIC_SO
XCS_MIC
MIC_SCK
XRST_RFML
HADR[0]
HADR[1]
HADR[2]
HADR[3]
HADR[4]
HADR[5]
HADR[6]
HADR[7]
HADR[8]
HADR[9]
HADR[10]
HADR[11]
HYI_PLL27IN
SWP
REFSWP
XCS_IC_801
XSRST_IC_801
ENC_XDEC
RCO2_EDFLD
RDX
WROX
HDAT[0]
HDAT[1]
HDAT[2]
HDAT[3]
HDAT[4]
HDAT[5]
HDAT[6]
HDAT[7]
XREC_ACT_M
XREC_ACT_P
BSD_IN
BSD_OUT
MIC_SI_EN
MIC_SI
MIC_SO
XCS_MIC
MIC_SCK
XRST_RFML
IOLVDD1
IOLVSS2
BS6
IOLVDD2
VDER
IOLVSS1
VBCK(6.75MHz)
BS1
BS0
BS5
RE_ST
BS4
BS3
BS2
RDY_FL
BS7
ARM_AVD1
ARM_AVD2
TBUSA0
TBUSA1
TBUSA3
TBUSA2
IOVDD1
INVDD1
TBUSA4
TBUSA5
TBUSA6
IOVSS1
INVSS1
TBUSA8
TBUSA9
TBUSA7
NC
IOVDD2
TBUSA12
TBUSA10
TBUSA11
TBUSA15
IOVSS2
TBUSA14
TBUSA13
ARM_TREQB
ARM_TREQA
ARM_TACK
IOVDD3
ARM_NTRST
ARM_TCK
IOVSS3
ARM_TDI
ARM_TDO
ARM_TMS
QTM1
AVD_PLL3
AVS_PLL3
IOVSS7
IOVDD8
AVD_PLLD
AVS_PLLD
AVD_PLLR
NC
COUT
AVS_PLLR
OSCBUF1
OSCBUF0
AVD_PLLP
AVS_PLLP
NC
DDVS1
VIN
VRT
AVDD1
AVSS1
DDVD1
VRB
PLLDIVRST
IOVDD7
PBRFD0
IOVSS6
INVDD3
PDO
PBRFD2
PBRFD5
IOVDD6
PBRFD4
TRFCLK
IOVSS5
PBRFD3
PBRFD1
RECA2
PCHCLK
RCHCLK
INVDD2
RECDT
IOVDD5
CTRL1
PCDCLK
IOVSS4
RCDCLK
INVSS2
MISOCLK
SYSRST
XSAVEOFF
QTM2
IOVDD4
PLLCK27O(27MHz)
IOVDD12
IOVSS11
HADR5
HADR7
HADR6
HADR4
HADR2
HADR3
HADR0
HADR1
IC_801RST
ROYALRST
SWP
BUSDIR
RFLID
RSWP
CEN
RDX
IOVDD11
WRX
HDIO7
IOVSS10
HDIO5
HDIO6
INVDD4
HDIO3
HDIO4
HDIO2
IOVDD10
HDIO0
HDIO1
IOVSS9
INVSS3
XRECAP
XRECAM
BSOUT
BSIN
IOVDD9
SINT
HI_SO
IOVSS8
HI_CS
HI_CLK
HI_SI
TMS
TDO
TRST
TDI
TCK
TEN
TEST0
AVD_DRAM10
AVS_DRAM10
NC
HADR9
HADR10
HADR11
HADR8
FRMREF
IOVSS12
MCK27M(27MHz)
SYCLK(27MHz)
INVSS4
NC
IC_601DT3
IOVDD14
IC_601DT0
IC_601DT7
IOVDD13
IC_601DT1
IC_601DT2
TFP
IC_601ACC
IC_601DEN
AVS_DRAM8
AVD_DRAM6
AVS_DRAM6
AVD_DRAM8
IOVSS13
IC_601DT4
IC_601DT5
IC_601DT6
BBFRST
IC_601DIR
AEDE
ABCK(6.75MHz)
IOVDD15
IOVSS14
AEDI
IOVSS15
INVSS5
ADDO
AVD_DRAM0
AVS_DRAM0
AVS_DRAM4
AVD_DRAM4
INVDD5
ADDE
AFS
AVD_DRAM2
AVS_DRAM2
NC
NC
10
D
14
5
2
M
I
12
XX MARK:NO MOUNT
C
3
4
J
L
G
9
VC-333 BOARD (6/18)
11
F
8
N
15
6
H
E
7
13
K
MUX/DEMUX, MPEG STREAM CONTROL
05
B
IC801
MPEG STREAM CONTROL
MUX/DEMUX,
(18/18)
123
(3/18)
50
(12/18)
115
46
(3/18)
(12/18)
125
118
(12/18)
119
(12/18)
120
(14/18)
(10/18)
121
122
(12/18)
(7/18)
124
106
(5/18)
20
(1/18)
REC
Ref.signal
REC/PB
PB
VIDEO SIGNAL
REC
SERVO
SIGNAL PATH
SIGNAL
VIDEO/AUDIO/
AUDIO
SIGNAL
PB
Y/CHROMA
SIGNAL PATH
(5/18)
103
(12/18)
112
48
(3/18)
(3/18)
105
(3/18)
86
(3/18)
54
(5/18)
49
(8/18)
114
4-21
4-22
VC-333 (6/18)
4-2. SCHEMATIC DIAGRAMS
VC-333 BOARD SIDE A
VC-333 BOARD SIDE B
4-2. SCHEMATIC DIAGRAMS
VC-333 BOARD SIDE A
VC-333 BOARD SIDE B
For Schematic Diagram
• Refer to page 4-67 for printed wiring board.
• Refer to page 4-67 for printed wiring board.
DCR-IP1/IP1E
:Voltage measurment of the CSP ICs
and the Transistors with mark,are
not possible.
and the Transistors with mark,are
not possible.
R:REC MODE
P:PB MODE
NO MARK:REC/PB MODE
R2/
P1.5
P1.5
R1.5/
P0.9
R2/P1.5
R1.5/
P0.9
R2/P1.5
R2/
P1.5
P1.5
9
570 mVp-p
5 msec (200 Hz)
2.7 Vp-p
20 msec (50 Hz)
q;
C1102 (IC1101
rj
) PB
Q1103
C
,
E
, Q1104
C
,
E
REC
470p
C1108
0.01u
C1107
PB_DATA
±
0.5%
R1107
6800
REG_GND
0.01u
C1113
0.01u
C1102
10uH
L1101
±
0.5%
R1105
18k
0.01u
C1110
SW_PS
RECA1
IC_1101_MODE
0.01u
C1105
RECDT
RECA2
6.3V
10u
C1101
10uH
L1103
RECCLK
0.01u
C1109
CTRL1
RP_2.8V
±
0.5%
22k
R1104
RF_OUT
RP_4.6V
0.01u
C1106
0.01u
C1111
10V
10u
C1104
±
0.5%
22k
R1109
3900
R1115
2SA1965-S-TL
Q1104
XREC_ACT_M
3900
R1114
2SA1965-S-TL
Q1103
XREC_ACT_P
R1106
15k
R1108
8200
0.1u
C1112
RP_6.0V
XX
L1102
330
R1101
UNRL21300AS0
Q1101
1
4
3
2
UNRL21300AS0
Q1102
1
4
3
2
CXA3619GA-T6
IC1101
123456789
1
0
1
1
1
2
1
3
1
4
1
5
1
6
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
R1116
180
R1117
180
R1118
0
0.01u
C1610
FG_REF2
BH2223GLU-E2
IC1602
1
NC
2
AO4
3
AO5
4
NC
5
AO6
6
AO7
7
AO8
8
NC
9
AO9
10
NC
11
NC
12
VCC
13
NC
14
AO10
15
NC
16
LD
17
NC
18
NC
19
NC
20
CLK
21
DI
22
NC
23
A01
24
GND
25
NC
26
NC
27
AO2
28
AO3
CAM_SCK
T_FG_OFST
CAM_SO
DA_STRB
FG_REF1
AMPGAIN
E_CFG_OFST
A_2.8V
10uH
L1601
22u
4V
C1605
PW+
PW-
11P
CN102
1
PW+
2
PW-
3
GND
4
GND
5
REC_M/E
6
REC_M/S
7
GND
8
REC_P/E
9
REC_P/S
10
PB_IN
11
GND
1
A
RECA1
RECA1
RECA2
RECCLK
RECDT
RECA2
RECCLK
RECDT
GND
D1E
XE
YE
D2E
GND
GND
D2O
YO
XO
D1O
GND
XME/MP
VCC_HEAD
REC_PEAK_T
REC_PEAK_I_MP
REC_PEAK_I_ME
REC_IR_MP
REC_IR_ME
VCC_REC_4.6V
PB_IR
PB_FBDP
CE
CO
PB_X_OUT
GND
PB_Y_OUT
PB_RF_IN
VCC_PB_4.6V
TEST_OUT
GND
AGCTC_Ech
AGCTC_Och
AGC_EVR
PB_RF_OUT
LPF_f0
SW_PS
CTRL0
CTRL1
REC_A1
VCC_2.8V
REC_A2
MODE1
REC_CLK
MODE2
REC_DATA
VCC_D2.8V
TEST
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AMP
AMP
PB HEAD
PB HEAD
SWP
POWER
MCH
PCH
PCH
MCH
REC HEAD
REC HEAD
PCH
MCH
PB HEAD
PB HEAD
DRUM HEAD
DECK(1/2)
W100 MECHANISM
SWITCH
SWITCH
SWITCH
SWITCH
IC1101
REC/PB AMP
IC1602
EVR(D/A CONVERTER)
10
REC/PB AMP
9
D
5
12
G
13
VC-333 BOARD (7/18)
B
16
6
7
8
05
E
3
C
XX MARK:NO MOUNT
11
15
14
H
F
4
2
REC/PB
PB
Y/CHROMA
SIGNAL
PB
AUDIO
VIDEO SIGNAL
SIGNAL PATH
SIGNAL PATH
Ref.signal
SIGNAL
VIDEO/AUDIO/
SERVO
REC
REC
126
(18/18)
(14/18)
134
133
(12/18)
(13/18)
127
131
(13/18)
21
(1/18)
130
(14/18)
128
(12/18)
124
(6/18)
(12/18)
132
4-23
4-24
VC-333 (7/18)
For Schematic Diagram
• Refer to page 4-67 for printed wiring board.
• Refer to page 4-67 for printed wiring board.
4-2. SCHEMATIC DIAGRAMS
VC-333 BOARD SIDE A
VC-333 BOARD SIDE B
4-2. SCHEMATIC DIAGRAMS
VC-333 BOARD SIDE A
VC-333 BOARD SIDE B
Click on the first or last page to see other DCR-IP1 / DCR-IP1E service manuals if exist.