Sony DVP-S500D / DVP-S505D Service Manual ▷ View online
6-3
(5-4) Servo DSP Download
DSP (IC506) code area ROM/RAM discrimination
RAM: Program download
RAM: Program download
→
Revision data read
ROM: Revision data read
Error 04: Data read error
13: DSP data not ready
For the Mask ROM, no download can be executed. Download is
possible for the RAM only. ROM/RAM is discriminated by the
DBUSY signal of DSP (IC506) pin 4 after hardware reset. The
diagnosis provides exclusive download flag.
For this flag, download not executed
possible for the RAM only. ROM/RAM is discriminated by the
DBUSY signal of DSP (IC506) pin 4 after hardware reset. The
diagnosis provides exclusive download flag.
For this flag, download not executed
: 0
download already executed : 1
download error
download error
: 2
ROM/RAM is discriminated by the status of DBUSY signal after
hardware reset. If RAM, the servo control code is downloaded.
If no error is found, the version No. is read from address:200, and
displayed.
If ROM, the version No. is read from address:200 immediately.
Compare displayed data with existing data.
If RAM, “DSP Download Rev.=xxxx” is displayed.
If ROM, “DSP Mask ROM Rev.=xxxx” is displayed.
hardware reset. If RAM, the servo control code is downloaded.
If no error is found, the version No. is read from address:200, and
displayed.
If ROM, the version No. is read from address:200 immediately.
Compare displayed data with existing data.
If RAM, “DSP Download Rev.=xxxx” is displayed.
If ROM, “DSP Mask ROM Rev.=xxxx” is displayed.
(5-5) Servo DSP Register
(Program download)
→
Data write
→
Read matching check
Error 04: Data read error
05: Write/read data mismatch error
13: DSP data not ready
14: DSP download error
13: DSP data not ready
14: DSP download error
The download flag is checked, and if 0, the program is downloaded.
However, in the case of ROM, it is not downloaded.
Unless download error occurs, the content of address 200h of DSP
(IC506) is read for saving, then checking starts. In this check, 16
kinds of patterns are written to the address 200h by shifting 1 bit
each from 0x0001 toward the left, then they are read.
If write/read mismatch error occurred, checking can be repeated.
However, in the case of ROM, it is not downloaded.
Unless download error occurs, the content of address 200h of DSP
(IC506) is read for saving, then checking starts. In this check, 16
kinds of patterns are written to the address 200h by shifting 1 bit
each from 0x0001 toward the left, then they are read.
If write/read mismatch error occurred, checking can be repeated.
(5-6) Servo DSP Reset Line
Register write
→
Hard reset
→
Register read
Error 02: Reset error
13: DSP data not ready
14: DSP download error
14: DSP download error
In the case of RAM, this diagnosis checks that the register cannot
be read after hardware reset. Unless download error occurs, the
content of address 200h of DSP (IC506) is read, and after hard-
ware reset, the data is read again for comparison.
The check results in OK, if the register cannot be read, or data are
not matched even if it can be read. The reset error occurs if read
data are same as that before hardware reset.
In the case of ROM, whether the version No. is initialized by the
reset is checked. First, the version No. is read, then its comple-
ment is written.
After hardware reset, the data is read again and if it matches the
written data, the reset error occurs.
be read after hardware reset. Unless download error occurs, the
content of address 200h of DSP (IC506) is read, and after hard-
ware reset, the data is read again for comparison.
The check results in OK, if the register cannot be read, or data are
not matched even if it can be read. The reset error occurs if read
data are same as that before hardware reset.
In the case of ROM, whether the version No. is initialized by the
reset is checked. First, the version No. is read, then its comple-
ment is written.
After hardware reset, the data is read again and if it matches the
written data, the reset error occurs.
(6) Data Source
(6-2) Register in ARP (IC806)
Register write
→
Register read matching check
Error 05: Write/read data mismatch error
Data from “0x00” up to “0xff” are written to 12 registers where all
bits can be written and read, then read to check for matching.
If write/read mismatch error occurred, checking can be repeated.
bits can be written and read, then read to check for matching.
If write/read mismatch error occurred, checking can be repeated.
(6-3) Reset Line in ARP (IC806)
Register write
→
Hard reset
→
Register read
Error 02: Reset error
05: Write/read data mismatch error
After “0xfe” is written to the INTEN3 register, whether it is ini-
tialized to “0x00” by the reset pulse signal is checked.
To make sure, the written data is read to check for matching be-
fore reset is executed.
tialized to “0x00” by the reset pulse signal is checked.
To make sure, the written data is read to check for matching be-
fore reset is executed.
(6-4) DRAM (IC810) in ARP
ROM data
→
ARP (IC806)
→
DRAM (IC810)
→
ARP (IC806)
read matching check
Error 03: Data write error (ARP (IC806) is not enabled for data
writing)
04: Data read error (ARP (IC806) is not enabled for data
reading)
05: Write/read data mismatch error
ROM (IC803) patterns are copied to all areas to be checked. Each
time 256 bytes are copied, the addresses of copy source (ROM)
are returned by 254 bytes. In detail check, all areas are checked to
verify all bits in DRAM (IC810), then the inverted data are further
checked in the same manner. The bus width of ARP (IC806) is 16
bits. This check program displays addresses in 16 bits.
Overwriting by the shadow can be detected, as the data are written
to all areas, then read. In the detail check, all areas of RAM (IC802)
are checked twice by inverting the data, while in the simple check
one block is checked, then subsequent 4 blocks are skipped, and
also inverted data are not checked.
If write/read mismatch error occurred, checking can be repeated.
time 256 bytes are copied, the addresses of copy source (ROM)
are returned by 254 bytes. In detail check, all areas are checked to
verify all bits in DRAM (IC810), then the inverted data are further
checked in the same manner. The bus width of ARP (IC806) is 16
bits. This check program displays addresses in 16 bits.
Overwriting by the shadow can be detected, as the data are written
to all areas, then read. In the detail check, all areas of RAM (IC802)
are checked twice by inverting the data, while in the simple check
one block is checked, then subsequent 4 blocks are skipped, and
also inverted data are not checked.
If write/read mismatch error occurred, checking can be repeated.
(6-5) Interrupt Line in ARP (IC806)
Data transfer request
→
Data transfer stop interruption from ARP
(IC806)
Error 21: ARP (IC806) interruption is not detected
AC-3 audio data stored in ROM (IC803) are transferred to the
ARP (IC806), then the designated sector data output stop inter-
ruption from ARP (IC806) is detected.
To discriminate the Decrypt (IC811) interruption which is also
sent in the same line, the Decrypt (IC811) interruption is all masked.
ARP (IC806), then the designated sector data output stop inter-
ruption from ARP (IC806) is detected.
To discriminate the Decrypt (IC811) interruption which is also
sent in the same line, the Decrypt (IC811) interruption is all masked.
6-4
(6-6) Register in Decrypt IC (IC811)
Register write
→
Register read matching check
Error 05: Write/read data mismatch error
0x00 – 0xfc data (lower 2 bits are masked) are written to the inter-
rupt register, then read to check for matching.
If write/read mismatch error occurred, checking can be repeated.
rupt register, then read to check for matching.
If write/read mismatch error occurred, checking can be repeated.
(6-7) Reset of Decrypt IC (IC811)
Register write
→
Hard reset
→
Register read
Error 02: Reset error
05: Write/read data mismatch error
After “0xfc” is written to the interrupt register, whether it is ini-
tialized to “0x00” by the reset pulse signal is checked.
To make sure, the written data is read to check for matching be-
fore reset is executed.
tialized to “0x00” by the reset pulse signal is checked.
To make sure, the written data is read to check for matching be-
fore reset is executed.
(6-8) Interrupt Line in Decrypt IC (IC811)
ROM (IC803)
→
ARP (IC806)
→
Decrypt (IC811)
Error 22: Decrypt (IC811) interruption is not detected
AC-3 audio data stored in ROM (IC803) are transferred to the
Decrypt via ARP (IC806), then the reserved data interruption from
Decrypt (IC811) is detected.
To discriminate the ARP (IC806) interruption which is alsosent in
the same line, the ARP (IC806) interruption is allmasked.
Decrypt via ARP (IC806), then the reserved data interruption from
Decrypt (IC811) is detected.
To discriminate the ARP (IC806) interruption which is alsosent in
the same line, the ARP (IC806) interruption is allmasked.
(6-9) Reserved Data Head Byte Reading
ROM (IC803)
→
ARP (IC806)
→
Decrypt (IC811) reserved data
head byte read matching check
Error 05: Write/read data mismatch error
22: Decrypt interruption is not detected
AC-3 audio data stored in ROM (IC803) are transferred to the
Decrypt via ARP (IC806), then the reserved data head bytes are
read from Decrypt (IC811) register.
As this audio data consists of 5 sectors, 0, 1, 2, 3, 4 data are writ-
ten at the head of reserved data of respective sectors.
Whether these data are matched is checked through every sector
interruption.
If write/read mismatch error occurred, checking can be repeated.
Decrypt via ARP (IC806), then the reserved data head bytes are
read from Decrypt (IC811) register.
As this audio data consists of 5 sectors, 0, 1, 2, 3, 4 data are writ-
ten at the head of reserved data of respective sectors.
Whether these data are matched is checked through every sector
interruption.
If write/read mismatch error occurred, checking can be repeated.
(7) AV Decoder (IC203)
(7-2) Register in 64020
Register write
→
Register read matching check
Error 05: Write/read data mismatch error
“0x00” – “0xff” data are written to 51 registers where all bits can
be written/read, then they are read to check for matching.
If write/read mismatch error occurred, checking can be repeated.
be written/read, then they are read to check for matching.
If write/read mismatch error occurred, checking can be repeated.
(7-3) Reset Line in 64020
Register write
→
Hard reset
→
Register read matching check
Error 02: Reset error
05: Write/read data mismatch error
After “0xff” is written to the Capture/Compare Control Register
0, whether it is initialized to “0x00” by the reset pulse signal is
checked.
To make sure, the written data is read to check for matching be-
fore reset is executed.
0, whether it is initialized to “0x00” by the reset pulse signal is
checked.
To make sure, the written data is read to check for matching be-
fore reset is executed.
(7-4) DREQ Signal Line in 64020
AV Decoder (IC203) DMA check
Error 03: Data write error
04: Data read error
05: Write/read data mismatch error
06: DMA transfer DREQ error
07: DMA transfer address error
05: Write/read data mismatch error
06: DMA transfer DREQ error
07: DMA transfer address error
The connection of DREQ signal line to the AV Decoder (IC203)
is checked through DMA transfer.
If no error is found in DMA transfer, the transferred data are com-
pared with the DRAM (IC810) data read from the register.
is checked through DMA transfer.
If no error is found in DMA transfer, the transferred data are com-
pared with the DRAM (IC810) data read from the register.
(7-5) DRAM in 64020
ROM data
→
AV Decoder (IC203)
→
DRAM (IC810)
→
AV De-
coder (IC203) read matching check
Error 03: Data write error
04: Data read error
05: Write/read data mismatch error
06: DMA transfer DREQ error
07: DMA transfer address error
05: Write/read data mismatch error
06: DMA transfer DREQ error
07: DMA transfer address error
ROM (IC803) patterns are copied to all areas to be checked. Be-
cause of large DRAM (IC810) capacity, each time 256 bytes are
copied, the addresses of copy source (ROM) are returned by 255
bytes. In detail check, to verify all bits in DRAM (IC810), the bit
patterns are checked again after inversion. DMA is used when
writing/reading the data. Though the bus width of AV Decoder
(IC203) is 64 bits, the display is given in 8 bits. Namely, actual
address is 1/8 of displayed data, and lower 3 bits indicate the byte
position.
Overwriting by the shadow can be detected, as the data are written
to all areas, then read. In the detail check, all areas of RAM are
checked twice by inverting the data, while in the simple check one
block is checked, then subsequent 4 blocks are skipped, and also
inverted data are not checked.
If write/read mismatch error occurred, checking can be repeated.
cause of large DRAM (IC810) capacity, each time 256 bytes are
copied, the addresses of copy source (ROM) are returned by 255
bytes. In detail check, to verify all bits in DRAM (IC810), the bit
patterns are checked again after inversion. DMA is used when
writing/reading the data. Though the bus width of AV Decoder
(IC203) is 64 bits, the display is given in 8 bits. Namely, actual
address is 1/8 of displayed data, and lower 3 bits indicate the byte
position.
Overwriting by the shadow can be detected, as the data are written
to all areas, then read. In the detail check, all areas of RAM are
checked twice by inverting the data, while in the simple check one
block is checked, then subsequent 4 blocks are skipped, and also
inverted data are not checked.
If write/read mismatch error occurred, checking can be repeated.
6-5
(7-6) Connection from ARP (IC806) to 64020
ROM data
→
ARP (IC806)
→
Decrypt (IC811)
→
AV Decoder
(IC203)
Error 04: Data read error
05: Write/read data mismatch error
06: DMA transfer DREQ error
07: DMA transfer address error
10: Chip-to-chip data transfer error
06: DMA transfer DREQ error
07: DMA transfer address error
10: Chip-to-chip data transfer error
AC-3 audio data stored in ROM (IC803) are written to the ARP
(IC806), then whether they are transferred to the AV Decoder
(IC203) is checked. If transfer error is not detected, the address of
AV Decoder (IC203) to which data are transferred is displayed on
the terminal.
A part of data transferred to the AV Decoder (IC203) is read into
Syscon RAM (IC802) through DMA, and compared with ROM
(IC803) data.
(IC806), then whether they are transferred to the AV Decoder
(IC203) is checked. If transfer error is not detected, the address of
AV Decoder (IC203) to which data are transferred is displayed on
the terminal.
A part of data transferred to the AV Decoder (IC203) is read into
Syscon RAM (IC802) through DMA, and compared with ROM
(IC803) data.
(7-7) Interrupt Line in 64020
AV Decoder DRAM (IC201, 202)
→
(DMA COPY) AV Decoder
DRAM (IC201, 202) another area
Error 31: AV Decoder interruption is not detected
Data transfer stop interruption which is generated through
DMA copy of DRAM (IC201, 202) data in AV Decoder (IC203)
to another area is detected.
DMA copy of DRAM (IC201, 202) data in AV Decoder (IC203)
to another area is detected.
(8) Video Consumption Concerned
(8-2) 1914 (Serial)
Color bar output (color bar enable command) from Video Encoder
(IC252)
(IC252)
Error 11: Serial transfer error
Using the Vsync interruption, serial communication to the Video
Encoder (IC252) starts, and the color bar enable command is trans-
ferred to the 1914.
The Vsync interruption and internal serial 1 interruption are used.
If no error is found, the message is displayed to prompt for key
entry.
Check the color bar output.
Encoder (IC252) starts, and the color bar enable command is trans-
ferred to the 1914.
The Vsync interruption and internal serial 1 interruption are used.
If no error is found, the message is displayed to prompt for key
entry.
Check the color bar output.
(8-3) 1914 Read
ID read
→
Existing data matching check
Error 40: 1914 ID error
The 1914 device ID is read.
Error if the read value is not “1914 (hex)”.
Error if the read value is not “1914 (hex)”.
(8-4) 1914 Vsync
CPU measures the 1914 Vsync interrupt cycle.
Error 41: Vsync interruption is not detected
42: Vsync interrupt cycle error
The number of interruption for 200 msec is counted, and if it is 11
to 13 times, this check is OK. It should be 12 times exactly, but ±1
errors are allowable.
to 13 times, this check is OK. It should be 12 times exactly, but ±1
errors are allowable.
(8-5) Still Picture Output (SDRAM (IC201,202) direct write)
Pattern data
→
AV Decoder (IC203)
→
Video Out
Error 31: AV Decoder (IC203) interruption (DMA transfer) is
not detected
The pattern is directly written to the SDRAM (IC201, 202) in AV
Decoder (IC203), then its picture display is checked.
First, the brightness signal data are written by the amount of one
screen while changing every pixel.
For the color difference signals, both Cr and Cb are set to 80h for
monochromic pictures, and the display is turned on.
Then, color difference signal data are written while changing the
data every column.
As both brightness signal data and color difference signal data
take regular patterns, the processing speed is increased through
DMA transfer of the repeated sections.
Further, in detail check the color difference signal data written to
the out of display area are copied through DAM transfer to change
display colors successively.
If no error is found, the message is displayed to prompt for key
entry.
Check the pattern output.
Decoder (IC203), then its picture display is checked.
First, the brightness signal data are written by the amount of one
screen while changing every pixel.
For the color difference signals, both Cr and Cb are set to 80h for
monochromic pictures, and the display is turned on.
Then, color difference signal data are written while changing the
data every column.
As both brightness signal data and color difference signal data
take regular patterns, the processing speed is increased through
DMA transfer of the repeated sections.
Further, in detail check the color difference signal data written to
the out of display area are copied through DAM transfer to change
display colors successively.
If no error is found, the message is displayed to prompt for key
entry.
Check the pattern output.
(8-6) Still Picture Output (via ARP (IC806))
ROM picture data
→
ARP (IC806)
→
AV Decoder (IC203)
→
Video Out
Error 10: Chip-to-chip data transfer error
ROM (IC803) data are transferred to the AV Decoder (IC203) via
ARP (IC806), and the displayed picture is checked.
If no error is found, the message is displayed to prompt for key
entry.
The output picture is same as the start-up picture.
ARP (IC806), and the displayed picture is checked.
If no error is found, the message is displayed to prompt for key
entry.
The output picture is same as the start-up picture.
(8-7) DNR (Serial) (IC251)
ROM picture data
→
ARP (IC806)
→
AV Decoder (IC203)
→
DNR (IC251)
→
Video Out (outline)
Error 10: Chip-to-chip data transfer error
Using special diagnostic command, the output still picture is trans-
ferred to the DNR (IC251) for checking.
If no error is found, the message is displayed to prompt for key
entry.
This checking is made only for the players with DNR.
The output picture used is same as that in (8-6) Still Picture Out-
put.
The colors will vary extremely, if DNR (IC251) is effective.
For the players without DNR (IC251), the error code 0 is returned.
ferred to the DNR (IC251) for checking.
If no error is found, the message is displayed to prompt for key
entry.
This checking is made only for the players with DNR.
The output picture used is same as that in (8-6) Still Picture Out-
put.
The colors will vary extremely, if DNR (IC251) is effective.
For the players without DNR (IC251), the error code 0 is returned.
6-6
(8-8) S Terminal DC Check
Color bar output by Video Encoder (IC252)
Error 11: Serial transfer error
The color bars are output in the same manner as in (8-2).
After VS signal is turned on/off repeatedly two times, the color
bar output is turned off.
After VS signal is turned on/off repeatedly two times, the color
bar output is turned off.
(9) Audio Concerned
(9-2) Sampling Frequency 44.1kHz
16.9344MHz oscillation
Error 37: PLL DAC (IC209) serial transfer interruption is not de-
tected
Sampling frequency 44.1kHz is set to the PLL DAC (IC209).
If no error is found, the message is displayed to prompt for key
entry.
Observe the output waveform of IC209 (CXD8696R) SCK02 pin.
If no error is found, the message is displayed to prompt for key
entry.
Observe the output waveform of IC209 (CXD8696R) SCK02 pin.
(9-3) Sampling Frequency 48kHz
18.4320MHz oscillation
Error 37: PLL DAC (IC209) serial transfer interruption is not de-
tected
Sampling frequency 48kHz is set to the PLL DAC (IC209).
If no error is found, the message is displayed to prompt for key
entry.
Observe the output waveform of IC209 (CXD8696R) SCK02 pin.
If no error is found, the message is displayed to prompt for key
entry.
Observe the output waveform of IC209 (CXD8696R) SCK02 pin.
(9-4) Sampling Frequency 96kHz
36.8640MHz oscillation
Error 37: PLL DAC (IC209) serial transfer interruption is not de-
tected
Sampling frequency 96kHz is set to the PLL DAC (IC209).
If no error is found, the message is displayed to prompt for key
entry.
Observe the output waveform of IC209 (CXD8696R) SCK02 pin.
If no error is found, the message is displayed to prompt for key
entry.
Observe the output waveform of IC209 (CXD8696R) SCK02 pin.
(9-5) Audio Digital Output
ROM audio data
→
ARP (IC806)
→
AV Decoder (IC203)
→
Digi-
tal audio I/F output
Error 10: ARP (IC806)
→
AV Decoder (IC203) data transfer
error
37: PLL DAC (IC209) serial transfer interruption is not de-
tected
AC-3-audio bit stream data stored in ROM (IC803) are transferred
to the AV Decoder (IC203) via ARP (IC806), and output to the
digital audio interface.
If no error is found, the message is displayed to prompt for key
entry.
Analog outputs are muted.
to the AV Decoder (IC203) via ARP (IC806), and output to the
digital audio interface.
If no error is found, the message is displayed to prompt for key
entry.
Analog outputs are muted.
(9-6) Audio Digital Mute
ROM audio data
→
ARP (IC806)
→
AV Decoder (IC203)
→
Digi-
tal Audio I/F output
Error 10: ARP (IC806)
→
AV Decoder (IC203) data transfer
error
37: PLL DAC (IC209) serial transfer interruption is not de-
tected
AC-3-audio bit stream data stored in ROM (IC803) are transferred
to the AV Decoder (IC203) via ARP (IC806), and output to the
Digital Audio Interface. In such a case, the mute signal is turned
on/off alternately while the data are output 4 times.
1st time : Mute off
to the AV Decoder (IC203) via ARP (IC806), and output to the
Digital Audio Interface. In such a case, the mute signal is turned
on/off alternately while the data are output 4 times.
1st time : Mute off
Audible
2nd time : Mute on
Not audible
3rd time : Mute off
Audible
4th time : Mute on
Not audible
If no error is found, the message is displayed to prompt for key
entry.
entry.
(9-7) MPEG Audio Analog Output
ROM audio data
→
ARP (IC806)
→
AV Decoder (IC203)
→
2ch
DAC (IC215)
→
Analog audio output
Error 10: ARP (IC806)
→
AV Decoder (IC203) data transfer
error
35: 2ch DAC (IC215) serial transfer interruption is not de-
tected
37: PLL DAC (IC209) serial transfer interruption is not de-
tected
MPEG-audio bit stream data stored in ROM (IC803) are trans-
ferred to the AV Decoder (IC203) via ARP (IC806), and analog
audio data are output from 2ch DAC (IC215).
If no error is found, the message is displayed to prompt for key
entry.
ferred to the AV Decoder (IC203) via ARP (IC806), and analog
audio data are output from 2ch DAC (IC215).
If no error is found, the message is displayed to prompt for key
entry.
(9-8) Dual DAC (Serial)
ROM audio data
→
ARP (IC806)
→
AV Decoder (IC203)
→
2ch
DAC (IC215)
→
Analog audio output (Attenuation)
Error 10: ARP (IC806)
→
AV Decoder (IC203) data transfer
error
35: 2ch DAC (IC215) serial transfer interruption is not de-
tected
37: PLL DAC (IC209) serial transfer interruption is not de-
tected
MPEG-audio bit stream data stored in ROM (IC803) are trans-
ferred to the AV Decoder (IC203) via ARP (IC806), and they are
attenuated by 12dB (–12dB) in the 2ch DAC (IC215), then analog
audio data are output.
If no error is found, the message is displayed to prompt for key
entry.
ferred to the AV Decoder (IC203) via ARP (IC806), and they are
attenuated by 12dB (–12dB) in the 2ch DAC (IC215), then analog
audio data are output.
If no error is found, the message is displayed to prompt for key
entry.
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