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(4-3)   Drvcon common RAM (IC138) check

IC093 (Syscon ROM) 

n IC138 (common RAM) collating check

Checking range: 0x03000001 - 0x03000fff

After confirming that the RAM areas common to Drvcon are not
occupied by Drvcon (namely, the contents of common RAM ad-
dresses are true), the IC093 (Syscon RAM) codes are copied to  the
IC138 (common RAM) areas from address 1, then the data are read
for checking. If all are same, the IC093 code bits are inverted and
checked again. If compared data are not same, a checking is sus-
pended, and error code 05, its address, written data, and read data
are displayed.
After checking, reset the Drvcon because irregular values are writ-
ten to the IC138.

If common RAM areas are occupied by Drvcon and they are not
opened even after about 2 seconds, the write error 03 is output.

(4-4)   Drvcon data exchange check

IC090 (Syscon) 

n IC136 (Drvcon), IC136 (Drvcon) n IC090

(Syscon) command path check

The path check command is sent from IC090 (Syscon) to IC136
(Drvcon), and as a result, whether the data same as sent data is
returned to the IC138 (common RAM) is checked. In the Syscon
Diagnosis, only the ROM revision is displayed. If no response is
returned from Drvcon or the data are not same, the error code 73 is
output.

(4-5)   Drvcon interrupt line check

IC136 (Drvcon) 

n IC090 (Syscon), IC090 (Syscon) n IC136

(Drvcon) interrupt line check

If CXD8663Q check command is sent from IC090 to IC136, the
IC136 returns IC181 (CXD8663Q) register read/write command.
Receiving this command, the IC090 outputs a response signal im-
plying that the interrupt signal was received, then the IC136 con-
firms this signal input and writes the Command Done to the IC138
(common RAM).
When the Command Done is not returned even after 1 second, the
error code 70 (DRV INT is not detected) is output if the interrupt
signal has not been received, or the error code 71 (Drvcon does not
recognize SYS INT) is output if the interrupt signal has been re-
ceived.
Also, upon detection of an error in IC181 (CXD8663Q) by this
command, the error code 30 is output.

If DRV INT signal is kept “low”, the Syscon repeats an interrupt
processing continuously, thus making error display impossible. For
this reason, only for this command, the Drvcon returns the DRV
INT signal to “high” even if SYS INT is not detected.  (The Syscon
makes judgment whether Command Done is returned or not.)
Here, if the Syscon makes no response, the DRV INT signal itself
will be faulty.

(4-6)   Drvcon SRAM check

IC090 (Syscon) 

n IC136 (Drvcon) check request command

The SRAM check command is sent from IC090 to IC136, and its
response result is displayed.
In case of an error, the error information of Drvcon is read, then the
error code 05, error address, written data, and read data are dis-
played.

(4-7)   EEPROM check

IC090 (Syscon) 

n IC136 (Drvcon) check request command

The EEPROM check command is sent from IC090 to IC136, and
its response result is displayed.
The error code 74 when IC139 (EEPROM) write signal is not ready,
or error code 05 when written data and read data are not same, error
address, written data, and read data are displayed.

(4-8)   RF Processor check

IC090 (Syscon) 

n IC136 (Drvcon) check request command

The RF processor check command is sent from IC090 to IC136,
and its response result is displayed.
In case of an error in IC770 (RF processor), the error code 76 is
output.

(4-9)   CXD2545 RAM check

The CXD2545 check command is sent from IC090 to IC136, and
its response result is displayed.
In case of an error in IC717 (CXD2545), the error code 75 is out-
put.

(4-10)   Drvcon ROM check

IC090 

n IC136 check request command

The EPROM check command is sent from IC090 to IC136.
The Drvcon calculates checksum of IC140 (EPROM), and returns
its result and the checksum value is displayed, if there is no error.
Compare the result displayed on the screen with the checksum of
original EPROM.

(4-11)   VCO offset automatic adjustment

IC090 

n IC136 check request command

The VCO offset automatic adjust command is sent from IC090 to
IC136.
If automatic adjustment failed, the error code 77 is output.

(5)   Data supply system

(5-2) IC217 (CXD8598R) reset check

Write to register 

n Hard reset n Read from register

Registers to be checked: TSC2 (0x06200011)

TSC1 (0x06200012)
TSC0 (0x06200013)

Data other than 0 are written to readable and writable registers in
IC217 (CXD8598R), and they are read after hard reset, then the
error code 02 is output if they are not cleared to 0.

(5-3)   IC217 (CXD8598R) register check

Register write 

n Register read collating check

Registers to be checked: TSC2 (0x06200011)

TSC1 (0x06200012)
TSC0 (0x06200013)

Incrementing 1 each starting from 0, data are written to readable
and writable registers, then they are read for checking. Incrementing
initial value by 1 each, a check is repeated 256 times.
If compared data are not same, a checking is suspended, and error
code 05, its address, written data, and read data are displayed.

(5-4)   IC181 (CXD8663Q) reset check

Write to register 

n Hard reset n Read from register

Register to be checked: INTRMASK (0x22)

Data other than 0 are written to readable and writable register in
IC181 (CXD8663Q), and they are read after hard reset, then the
error code 02 is output if they are not cleared to 0.

(5-5)   IC181 (CXD863Q) register check

Register write 

n Register read collating check

Register mask data to be checked

0x20

0xbf

0x22

0xff

0x25

0xff

0x26

0xff

0x27

0xff

Incrementing 1 each starting from 0, data are written to readable
and writable registers, then they are read for checking. Incrementing
initial value by 1 each, a check is repeated 256 times. However,
some bits that cannot be written are masked.
If compared data are not same, a checking is suspended, and error
code 05, its address, written data, and read data are displayed.

(5-6)   IC181 (CXD8663Q) DRAM check

ROM 

n IC181 (CXD8663Q) n DRAM n  IC181 (CXD8663Q)

read collating check

Checking range: 0x00000000 - 0x0007ffff

ROM pattern is copied to all areas to be checked. Each time 256
bytes are copied, 255 bytes of original (ROM) address are returned.
A reading check is made after data are written to all areas.
If compared data are not same, a checking is suspended, and error
code 05, its address, written data, and read data are displayed.

(5-7)   IC181 (CXD8663Q) interrupt line check

IC093 (Syscon ROM) 

n  IC181 (CXD8663Q) n IC217

(CXD8598R)

DVD bit stream data stored in IC093 are transferred to the IC182
(external DRAM of IC181), and the SD bus sector header detect
interruption is checked, which occurs by flowing data to the IC217
(CXD8598R).
If the header of SD bus sector in IC181 (CXD8663Q) is not
detected, the error code 31 is output.

As SERR signal from IC181 (CXD8663Q) to IC217 (CXD8598R)
is not initialized, this signal line is shut off and fixed to “high” be-
fore checking.

(5-8)   IC181 (CXD8663Q) to IC217 (CXD8598R) connection check

IC093 (Syscon ROM) 

n  IC181 (CXD8663Q) n  IC217

(CXD8598R)

DVD bit stream data stored in IC093 are transferred to the IC182
(external DRAM of IC181), and IC217 (CXD8598R) transfer end
interruption is checked, which occurs by flowing data to the IC217
(CXD8598R).  If the transfer end interruption is not detected, the
error code 21 is output.
As SERR signal from IC181 (CXD8663Q) to IC217 (CXD8598R)
is not initialized, this signal line is shut off and fixed to “high” be-
fore checking.

(5-9)   IC184 (CXD8669AQ) reset check

Write to register 

n Hard reset  n Read from register

Register to be checked: SYSINI (0xe1)

Data other than 0 are written to readable and writable register in
IC184 (CXD8669AQ), and they are read after hard reset, then the
error code 02 is output if they are not cleared to 0.

(5-10)   IC184 (CXD8669AQ) register check

Register write  

n Register read collating check

Register mask data to be checked

0xe0

0x80

0xe1

0xff

0xe4

0xc0

0xe5

0xc0

0xe6

0xf8

Incrementing 1 each starting from 0, data are written to readable
and writable registers, then they are read for checking. Incrementing
initial value by 1 each, a check is repeated 256 times. However,
some bits that cannot be written are masked.
If compared data are not same, a checking is suspended, and error
code 05, its address, written data, and read data are displayed.

(5-11)   IC216 (CXD1186) reset check

Write to register 

n Hard reset n Read from register

Registers to be checked: DADRC_L (0x06380007)

DADRC_H (0x06380008)
HXFRC_L (0x06380009)
HXFRC_H (0x0638000A)
HADRC_L (0x0638000B)
HADRC_H (0x0638000C)

Data other than 0 are written to readable and writable register in
IC216 (CXD1186), and they are read after hard reset, then the error
code 02 is output if they are not cleared to 0.

(5-12)   IC216 (CXD1186) register check

Register write 

n Register read collating check

Registers to be checked: DADRC_L (0x06380007)

DADRC_H (0x06380008)
HXFRC_L (0x06380009)
HXFRC_H (0x0638000A)
HADRC_L (0x0638000B)
HADRC_H (0x0638000C)

Incrementing 1 each starting from 0, data are written to readable
and writable registers, then they are read for checking. Incrementing
initial value by 1 each, a check is repeated 256 times.
If compared data are not same, a checking is suspended, and error
code 05, its address, written data, and read data are displayed.

(5-13)   IC216 (CXD1186) SRAM check

IC093 (Syscon ROM) 

n IC216 (CXD1186) n IC215 (SRAM)

n IC216 read collating check

Checking range: 0x00000000 - 0x00007fff

IC093 ROM pattern is copied to all areas to be checked. Each time
256 bytes are copied, 255 bytes of original (ROM) address are re-
turned. A reading check is made after data are written to all areas.
After SRAM write addresses are set, error code 03 when writing is
not ready, or after read addresses are set, error code 04 when read-
ing is not ready is output, then a check is finished.
Also, if compared data are not same, a check is suspended, and
error code 05, its address, written data, and read data are displayed.

(5-14)   IC216 (CXD1186) to IC217 (CXD8598R) connection check

IC093 (ROM) 

n IC216 (CXD1186) n IC217 (CXD8598R)

VCD bit stream data stored in IC093 are transferred to the IC215
(external SRAM of IC216), and IC217 (CXD8598R) transfer end
interruption is checked, which occurs by flowing data to the IC217
(CXD8598R).
If the transfer end interruption is not detected, the error code 21 is
output.
Further, SCR is read to check its value. If the value is not the one in
sector transferred, the error code 22 is output.

(6)   Video Decoder

(6-2)   IC281 (CXD1900BQ) reset check

Write to register  

n Hard reset n Read from register

Register to be checked: PLYMOD (0x06080002)

Data other than 0 are written to readable and writable register in
IC281 (CXD1900BQ), and they are read after hard reset, then the
error code 02 is output if they are not cleared to 0.

(6-3)   IC281 (CXD1900BQ) register check

Register write 

n Register read collating check

Register to be checked: PLYMOD (0x06080002)

Incrementing 1 each starting from 0, data are written to readable
and writable register, then they are read for checking. Incrementing
initial value by 1 each, a check is repeated 256 times. However,
some bits that cannot be written are masked.
If compared data are not same, a checking is suspended, and error
code 05, its address, written data, and read data are displayed.

(6-4)   IC281 (CXD1900BQ) DRAM check

IC093 (ROM) 

n IC281 n IC280, IC282 n NIC284 (DRAM)

n IC281 read collating check

Checking range: 0x00000000 - 0x0003ffff (data bus width = 64bits)

IC093 ROM pattern is copied to all areas to be checked. Because of
large DRAM capacity, each time 256 bytes are copied, 255 bytes of
original (IC093) address are returned.  A reading check is made
after data are written to all areas.
The error code 03 when writing is not ready, or error code 04 when
reading is not ready is output, then a check is finished.
Also, if compared data are not same, a check is suspended, and
error code 05, its address, written data, and read data are displayed.
However, the data are displayed every 8 bits, though the bus width
of IC281 (CXD1900BQ) is 64 bits.  Namely, actual address is the
displayed value shifted by 3 bits to the right where lower 3 bits
indicate the byte position.
For example, in the case of display shown below:

IC281 (CXD1900BQ) DRAM
    Error Code: 05
    Address: 000abcde
    Write Data: fb
    Read Data: ff

If displayed value 0 0 0 A B C D E is expressed with binary num-
ber, 0000 0000 0000 1010 1011 1100 1101 1110.
If it is shifted by 3 bits to the right, 0000 0000 0000 0001 0101 0111
1001 1011 110.  That is, assuming that the top of address 0 0 0 1 5
7 9 B in hexadecimal notation is 0th byte, the 6th byte is erroneous
such as FB 

n FF (as for the bit position in the same manner, the

53rd bit is 0 

n 1, assuming that MSB is 0th and LSB is 63rd).

(6-5)   CXD1914 VSync check

IC475 (CXD1914Q) VSync interrupt cycle measurement

The VSync interruption is enabled for about 160msec, and the num-
ber of VSync interruption from NTSC encoder is counted. The op-
eration is normal if the count is more than 9 times and less than 11
times.  If out of this range, the error code 41 is output.
The SCI1 interruption is also enabled, as the NTSC encoder pro-
cessing is required due to VSync interruption.

(6-6)   IC281 (CXD1900BQ) VSync interrupt line check

IC281 (CXD1900BQ) VSync interrupt detection check

The VSync interruption of IC281 (CXD1900BQ) is enabled and
whether interruption is made is checked.  If no interruption is made
though 2 seconds elapsed, the error code 41 is output.

(6-7)   IC217 (CXD8598R) to IC281 (CXD1900BQ) connection

check

IC093 

n IC216 n IC215 n IC216  n IC217 n IC281 n

IC280,
IC282 ~ NIC284

VCD bit stream data stored in IC093 are transferred via IC216
(CXD1186) to the IC215 (SRAM), and the sequence header inter-
ruption and transfer end interruption from IC281 are checked, which
occur by flowing data to the IC281 (CXD1900BQ) via IC216
(CXD1186) and IC217 (CXD8598R).
The error code 21 when transfer end interruption for transferred
sectors is not detected, or error code 42 when sequence header in-
terruption is not detected is output.

(7)   Subpictures

(7-2)   IC312 (CXD8600R) reset check

Write to register 

n Hard reset  n Read from register

Register to be checked: WRITE_READ_TOP (0x06000050)

Data other than 0 are written to readable and writable register in
IC312 (CXD8600R), and they are read after hard reset, then the
error code 02 is output if they are not cleared to 0.

(7-3)   IC312 (CXD8600R) register check

Register write 

n Register read collating check

Registers to be checked: VB_LUMINANCE   (0x06000050)

VB_LUMINANCE+1
VB_LUMINANCE+2
VB_LUMINANCE+3
VB_LUMINANCE+4
VB_LUMINANCE+5
VB_LUMINANCE+6
VB_LUMINANCE+7
VB_LUMINANCE+8
VB_LUMINANCE+9
VB_LUMINANCE+A
VB_LUMINANCE+B
VB_LUMINANCE+C
VB_LUMINANCE+D
VB_LUMINANCE+E
VB_LUMINANCE+F

The values written to the registers in IC312 (CXD8600R) are read
from the same address WRITE_READ_TOP in any registers. There-
fore, the Diagnosis function cannot read data after data were writ-
ten to all registers. A checking is made by reading every register.
If compared data are not same, a check is suspended, and error code
05, its address, written data, and read data are displayed.

(7-4)   IC312 (CXD8600R) SRAM check

IC093 (ROM)  

n IC312 (CXD8600R)  n  IC313, IC319 (SRAM)

n IC312 read collating check

Checking range: 0x00000001 - 0x0003ff000

The IC312 (CXD8600R) cannot designate read/write address of
SRAM.  Internal pointer manages the addresses automatically.  Ac-
cordingly, the reading order is same as the writing order.
IC093 pattern is copied to all areas to be checked. Each time 256
bytes are copied, 255 bytes of original (IC093) address are returned.
A reading check is made after data are written to all areas.  As the
Syscon Diagnosis is a simplified check, actual check range is 1/5 of
the above mentioned checking range.
Unlike other RAM checks, the addresses are not skipped. The ad-
dress 0 in each area has specific meaning, and therefore arbitrary
data cannot be written.
After the fixed data is written to address 0, a check starts from ad-
dress 1, and the last 255 bytes are not checked because of a compli-
cated program.
If compared data are not same, a check is suspended, and error code
05, its address, written data, and read data are displayed.
However, IC312 (CXD8600R) cannot designate an address, and
the repeat check is ignored.
Also, in case of an error in VB, 0x10000000 is added to the address
for explicit discrimination.

(7-5)   IC217 (CXD8598R) to IC312 (CXD8600R) connection check

IC093 (ROM)  

n IC181 (CXD8663Q)  n IC217 (CXD8598R)

n IC312 (CXD8600R)

The bit stream data including subpictures stored in IC093 (ROM)
are transferred to the IC182 (external DRAM of IC181). Then, SP
Arrive signal from IC312 is checked, which is generated by flow-
ing the data to the IC312 (CXD8600R) via IC217 (CXD8598R).
The error code 61 is output when data arrival cannot be confirmed
though 2 seconds elapsed after data transfer request was sent to the
IC181 (CXD8663Q).

As SERR signal from IC181 (CXD8663Q) to IC217 (CXD8598R)
is not initialized, this signal line is shut off and fixed to “high” be-
fore checking.
When an error occurred, confirm (5-8) IC181 (CXD8663Q) to IC217
(CXD8598R) connection check.

(7-6)   IC312 (CXD8600R) interrupt line check

IC093 (ROM)  

n IC181 (CXD8663Q)   n  IC217 (CXD8598R)

n IC312 (CXD8600R)

The bit stream data including subpictures stored in IC093 (ROM)
are transferred to the IC182 (external DRAM of IC181). Then, the
PTS interrupt is checked, which occurs by flowing the data to the
IC312 (CXD8600R) via IC217 (CXD8598R).
The error code 62 is output when an interruption cannot be con-
firmed though 2 seconds elapsed after data transfer request was
sent to the IC181 (CXD8663Q).
As SERR signal from IC181 (CXD8663Q) to IC217 (CXD8598R)
is not initialized, this signal line is shut off and fixed to “high” be-
fore checking.
When an error occurred, confirm (5-8) IC181 (CXD8663Q) to IC217
(CXD8598R) connection check.

(8)   Video Related