DOWNLOAD Sony DSC-F55 / DSC-F55E (serv.man2) Service Manual ↓ Size: 522.65 KB | Pages: 32 in PDF or view online for FREE

The system block diagram of the DSC-F55/F55E is as shown
in Fig. 1-2.

From 

Camera

Block

Address Bus

Data Bus

Operation 

Switches

Y

CR

CB

R

G

B

The amount of incident light that is introduced from the lens block enters
the CCD imager through iris.

The CCD imager is driven by the pulses (V1 to V4, H1, H2 and RG).  The
CCD output signal between the camera-through mode and the capture mode
is switched by the timing generator as it is controlled by the CAM/ME-
DIUM Controller.  In the camera-through mode, the CCD imager signal is
sampled to a quarter of the original information and is output.

The output signal from the CCD imager is sampled-and-held by the signals
(XSHP, XSHD) that are supplied from the timing generator.  The sample-
and-hold is performed in order to ensure operation of the A/D converter at
the latter circuit.  When the signal amplitude after sample-and-hold is small,
the signal is amplified by the AGC amplifier.

The digital R. G. B. output data from IC152 enters the CAMERA DSP
where the digital data is converted to Y, CR and CB.

The digital data in the form of Y, CR and CB are written into the SDRAM
with the data format of odd data and even data.
The digital data enters again into the CAMERA DSP where it is converted
to analog color difference signals (Y, CR and CB).

The output Y, CR and CB signals from the CAMERA DSP are converted to
the R, G and B signals in the LCD DRIVE circuit and drive the LCD.

VD

IC152

CCD IN

HD

Y

IC251

171 PIN

CB

IC251

174 PIN

CR

IC251

177 PIN

When the shutter button is pressed, the shutter is opened and the video
image equal to one video frame is introduced to the CCD imager and the
iris shutter is forcibly closed by the shutter drive circuit (IC201).

The CCD imager is driven by the pulses (V1 to V4, H1, H2 and RG).  In the
capture mode, the full amount of incoming information to the CCD imager
is output.

The same signal processing as in the camera-through mode is performed.

The A/D converter CCD output signal passes through the CAMERA DSP
at first and is written into the SDRAM (IC252) in the order of odd and even
signals.  When the digital signal is written into the SDRAM once, it is read
out from the SDRAM and sent to the CAMERA DSP where the digital
signal in the form of Y, CR and CB is processed.  It is then again written
into the SDRAM.  At this stage, the image data of 2,000,000 pixels is con-
structed.  While the 2,000,000 pixel data is being stored, the CAMERA
DSP uses it to create an image having fewer pixels to be displayed on the
LCD.  This smaller image data is written into the SDRAM (separately from
the 2,000,000 pixel data).  The smaller image data is once again D/A con-
verted by the CAMERA DSP to create an analog video signal for the LCD.
The 2,000,000 pixel data is compressed in JPEG format as directed by the
CAM/MEDIUM DSP.

The compressed JPEG data is written into the SDRAM (IC455).

The digital data that is written into the SDRAM (IC455) is converted from
parallel data to serial data by the memory stick interface in order to store
the digital data in the memory stick.

Because the CAM/MEDIUM Controller does not have built-in ROM, all
the camera control programs are saved in the FLASH ROM (IC454).  The
font data of OSD is also stored in the FLASH ROM.

The output image data from the memory stick is converted from serial data
to parallel data by the MEMORY STICK I/F IC (IC451) and written into
the SDRAM (IC455).  Then the output image data from the memory stick
takes two paths as directed by the CAM/MEDIUM Controller: One signal
passes through the CAM/MEDIUM Controller and enters the RS-232C
DRIVE IC (IC353).  This signal is then output from the DRIVE IC and is
sent to the DIGITAL I/O terminal of the DSC-F55/55E from which the
data is output to an external personal computer.  The other output is sent to
the CAMERA DSP where the compressed data is restored to the original
2,000,000 pixel data.

The 2,000,000 pixel data is written into the SDRAM (IC252) in the data
format of Y, CR and CB.  This data is read from the SDRAM and is sent to
the CAMERA DSP again to create the data for LCD display.  The pixel
data for LCD display is converted to VGA size and is once again written
into the SDRAM (IC252).  This data is D/A converted by the CAMERA
DSP again so that the Y, CR and CB signals are created to be displayed on
the LCD.