Sony DSC-F55 / DSC-F55E (serv.man2) Service Manual ▷ View online
3
BOARD LAYOUT DIAGRAMS
INVERTER TRANSFORMER UNIT
VL-27
(BACK UP BATTERY)
(BACK UP BATTERY)
DD-126
(DC-DC CONVERTER)
(DC-DC CONVERTER)
MM-39
(MEMORY)
(MEMORY)
SY-54
CAMERA, CAMERA DSP,
LCD DRIVE, TIMING GENERATOR,
VIDEO, SH DSP, SERIAL I/O,
AUDIO, LENS MOTOR DRIVE,
HI CONTROL
CAMERA, CAMERA DSP,
LCD DRIVE, TIMING GENERATOR,
VIDEO, SH DSP, SERIAL I/O,
AUDIO, LENS MOTOR DRIVE,
HI CONTROL
CD-224
(CCD IMAGER)
(CCD IMAGER)
FLASH UNIT
4
Fig. 1-1
1. SYSTEM CONTROL CIRCUIT
1-1. Overview
The DSC-F55/F55E system consists of two microprocessors (Human In-
terface (HI) Controller IC603 and Camera/Medium Controller IC351).
(IC501 is an auxiliary IC for serial communication between the control-
lers.)
The data transfer system between the controllers and block diagram are
shown in Fig. 1-1.
terface (HI) Controller IC603 and Camera/Medium Controller IC351).
(IC501 is an auxiliary IC for serial communication between the control-
lers.)
The data transfer system between the controllers and block diagram are
shown in Fig. 1-1.
Communication between the HI microprocessor (abbreviated as “HI Con-
troller” hereafter) and the camera/medium microprocessor (abbreviated as
“CAM/MEDIUM Controller” hereafter) is established using clock synchro-
nous serial communication.
When the HI Controller detects any key input, it sends the corresponding
mode command to the CAM/MEDIUM Controller in accordance with the
contents of key input. At the same time, the status of the camera block and
other blocks are always sent to the HI Controller. The HI Controller con-
trols the operating mode of the DSC-F55/F55E. The control data of the HI
Controller is saved in IC456 (EEPROM) and that of the CAM/MEDIUM
Controller is saved in IC457 (EEPROM).
troller” hereafter) and the camera/medium microprocessor (abbreviated as
“CAM/MEDIUM Controller” hereafter) is established using clock synchro-
nous serial communication.
When the HI Controller detects any key input, it sends the corresponding
mode command to the CAM/MEDIUM Controller in accordance with the
contents of key input. At the same time, the status of the camera block and
other blocks are always sent to the HI Controller. The HI Controller con-
trols the operating mode of the DSC-F55/F55E. The control data of the HI
Controller is saved in IC456 (EEPROM) and that of the CAM/MEDIUM
Controller is saved in IC457 (EEPROM).
IC351
CAM/MEDIUM
Controller
IC457
EEPROM
IC456
EEPROM
IC703
MELODY
IC603
HI Controller
IC501
SERIAL I/D
POWER SW
PLAY/MOVIE
/STILL SW
SHUTTER
SW
TIMER/
CLOCK
FUNCTION
SW
RESET
BUS
SERIAL
SERIAL
5
Fig. 1-2
1-2. System Block Diagram
The system block diagram of the DSC-F55/F55E is as shown
in Fig. 1-2.
in Fig. 1-2.
From
Camera
Block
IC251
Image
Processing
JPEG
IC802
RGB
Decoder
LCD
Display
IC252
SDRAM
64M Bit
Address Bus
Data Bus
IC455
SDRAM
16M
IC454
FLASH ROM
8M Bit
IC351
CAM/MEDIUM
Controller
IC457
EEPROM
IC501
IC451
MEMORY STICK
I/F
IC456
EEPROM
IC603
HI Controller
Memory Stick
Operation
Switches
Y
CR
CB
R
G
B
6
2. SIGNAL PROCESSING
2-1. Signal Processing in Camera-through Mode
CCD IMAGER (IC102)
The amount of incident light that is introduced from the lens block enters
the CCD imager through iris.
the CCD imager through iris.
The CCD imager is driven by the pulses (V1 to V4, H1, H2 and RG). The
CCD output signal between the camera-through mode and the capture mode
is switched by the timing generator as it is controlled by the CAM/ME-
DIUM Controller. In the camera-through mode, the CCD imager signal is
sampled to a quarter of the original information and is output.
CCD output signal between the camera-through mode and the capture mode
is switched by the timing generator as it is controlled by the CAM/ME-
DIUM Controller. In the camera-through mode, the CCD imager signal is
sampled to a quarter of the original information and is output.
S/H, AGC, A/D CONV (IC152)
The output signal from the CCD imager is sampled-and-held by the signals
(XSHP, XSHD) that are supplied from the timing generator. The sample-
and-hold is performed in order to ensure operation of the A/D converter at
the latter circuit. When the signal amplitude after sample-and-hold is small,
the signal is amplified by the AGC amplifier.
(XSHP, XSHD) that are supplied from the timing generator. The sample-
and-hold is performed in order to ensure operation of the A/D converter at
the latter circuit. When the signal amplitude after sample-and-hold is small,
the signal is amplified by the AGC amplifier.
CAMERA DSP (IC251)
The digital R. G. B. output data from IC152 enters the CAMERA DSP
where the digital data is converted to Y, CR and CB.
where the digital data is converted to Y, CR and CB.
SDRAM (IC252)
The digital data in the form of Y, CR and CB are written into the SDRAM
with the data format of odd data and even data.
The digital data enters again into the CAMERA DSP where it is converted
to analog color difference signals (Y, CR and CB).
with the data format of odd data and even data.
The digital data enters again into the CAMERA DSP where it is converted
to analog color difference signals (Y, CR and CB).
LCD DRIVE (IC802)
The output Y, CR and CB signals from the CAMERA DSP are converted to
the R, G and B signals in the LCD DRIVE circuit and drive the LCD.
the R, G and B signals in the LCD DRIVE circuit and drive the LCD.
