Sony XR-M500R / XR-M550 Service Manual ▷ View online
46
Pin No.
Pin Name
I/O
Description
78
NC
O
Not used (open)
79
KEYACK
I
Input of acknowledge signal for the key entry Acknowledge signal is input to accept function
and eject keys in the power off status On at input of “H”
and eject keys in the power off status On at input of “H”
80
AD ON
O
A/D converter power control signal output terminal
When the KEYACK (pin ul) that controls reference voltage power for key A/D conversion input
is active, “L” is output from this terminal to enable the input
When the KEYACK (pin ul) that controls reference voltage power for key A/D conversion input
is active, “L” is output from this terminal to enable the input
81
ACCIN
I
Accessory detection signal input terminal “L”: accessory on
82
FLS PWON
O
Power on/off control signal output of the illumination LED and liquid crystal display driver
(IC901, 902) “H”: power on
(IC901, 902) “H”: power on
83
PW-ON
O
Main system power supply on/off control signal output terminal “H”: power on
84
TESTIN
I
Setting terminal for the test mode “L”: test mode, Normally: fixed at “H”
85
RAMBU
I
Internal RAM reset detection signal input from the RN5VD33AA (IC603)
Input terminal to check that RAM data are not destroyed due to low voltage
This checking is made within 100 msec after reset
Input terminal to check that RAM data are not destroyed due to low voltage
This checking is made within 100 msec after reset
86
HSTX
I
Hardware standby input terminal “L”: hardware standby mode Reset signal input in this set
87
MD2
I
Setting terminal for the CPU operational mode (fixed at “L” in this set)
88
MD1
I
Setting terminal for the CPU operational mode (fixed at “H” in this set)
89
MD0
I
Setting terminal for the CPU operational mode (fixed at “H” in this set)
90
RESET
I
System reset signal input from the reset signal generator (IC602) and reset switch (S901, 902)
“L”: reset “L” is input for several 100 msec after power on, then it changes to “H”
“L”: reset “L” is input for several 100 msec after power on, then it changes to “H”
91
VSS
—
Ground terminal
92
X0
I
Main system clock input terminal (3.68 MHz)
93
X1
O
Main system clock output terminal (3.68 MHz)
94
VCC
—
Power supply terminal (+5V)
95
ILLIN
I
Auto dimmer control illumination line detection signal input terminal
“L” is input at dimmer detection
“L” is input at dimmer detection
96
I-DET
I
Detection signal input from the motor overload detection circuit for the front panel open/close
motor (M601)
“L” is input when the motor current exceeds the specified value
motor (M601)
“L” is input when the motor current exceeds the specified value
97
MOT–
O
Front panel open/close motor (M601) drive signal (in panel close direction) output to the
BA6288FS (IC502) “H” active *2
BA6288FS (IC502) “H” active *2
98
MOT+
O
Front panel open/close motor (M601) drive signal (in panel open direction) output to the
BA6288FS (IC502) “H” active *2
BA6288FS (IC502) “H” active *2
99
CLOSE SW
I
Front panel open/close detect switch input terminal “L” is input when the front panel is closed
100
OPEN SW
I
Front panel open/close detect switch input terminal “L” is input when the front panel is opened
101 to 103
SCODE0 to
SCODE3
I
Setting terminal for security code
104, 105
DSTSEL1,
DSTSEL2
I
Destination setting terminal (A/D input) XR-M500R: fixed at “L”, XR-M550: fixed at “H”
106
BOOT
O
Serial data output to the liquid crystal display drive controller (IC607)
107
DSP GAIN
O
Not used (open)
108
DSP ON
O
Power supply on/off control signal output terminal “H”: DSP on Not used (open)
109
NC
O
Not used (open)
110
EMPH-IN
I
Emphasis control signal input terminal Not used (open)
111
PACK SW
I
Cassette in/out detect switch (S901) “L”: cassette in
112
4V SEL
I
Input terminal of whether line driver is mounted or not is detected
“L”: line driver is mounted (XR-M550), “H”: line driver is not mounted (XR-M500R)
“L”: line driver is mounted (XR-M550), “H”: line driver is not mounted (XR-M500R)
113
P SEL
I
Power select input terminal Not used (fixed at “L”)
47
Pin No.
Pin Name
I/O
Description
114
TUNON
O
Tuner system power supply on/off control signal output terminal
“H”: tuner power on
“H”: tuner power on
115, 116
LED SW1,
LED SW2
O
Security/operation side select control signal output to the liquid crystal display drive controller
(IC607)
(IC607)
117, 118
NC
O
Not used (open)
119
VSS
—
Ground terminal
120
DOLBY
O
Dolby-B on/off select signal output to the CXA2510AQ (IC401) “H”: dolby on
*1 Loading/tape operation motor control
STOP
LOADING/
FORWARD
EJECT/
REVERSE
BRAKE
LM-LOD (pin ya )
“L”
“H”
“L”
“H”
LM-EJ (pin y; )
“L”
“L”
“H”
“H”
Terminal
Mode
*2 Front panel open/close motor (M601) control
STOP
FRONT PANEL
OPEN
FRONT PANEL
OPEN
BRAKE
MOT– (pin oj )
“L”
“L”
“H”
“H”
MOT+ (pin ok )
“L”
“H”
“L”
“H”
Terminal
Mode
48
•
MAIN BOARD IC607 HD6432355A22F (LIQUID CRYSTAL DISPLAY DRIVE CONTROLLER)
Pin No.
Pin Name
I/O
Description
1, 2
PG3, PG4
O
Not used (open)
3
VSS
—
Ground terminal
4
NC
—
Not used (open)
5
VCC
—
Power supply terminal (+5V)
6 to 9
PC0 to PC3
O
Not used (open)
10
VSS
—
Ground terminal
11 to 14
PC4 to PC7
O
Not used (open)
15 to 18
PB0 to PB3
O
Not used (open)
19
VSS
—
Ground terminal
20 to 23
PB4 to PB7
O
Not used (open)
24 to 27
PA0 to PA3
O
Not used (open)
28
VSS
—
Ground terminal
29 to 32
PA4/IRQ4 to
PA7/IRQ7
O
Not used (open)
33
SP-LAT
I
Serial data latch pulse input for spectrum display from the system controller (IC601)
“H” active
“H” active
34
P66/IRQ2
O
Not used (open)
35, 36
VSS
—
Ground terminal
37
P65/IRQ1
O
Not used (open)
38
BUS-ON
I
Bus on/off control signal output from the system controller (IC601)
“L”: bus on
“L”: bus on
39
VCC
—
Power supply terminal (+5V)
40
SPE-A
O
41
SPE-B
O
42
SPE-C
O
43
SPE-SEL
O
44
VSS
—
Ground terminal
45
DSP SEL
I
Spectrum analyzer display data select signal input from the BA3834F (IC102)
46, 47
LED SW1,
LED SW2
I
Security/operation side select control signal input from the system controller (IC601)
“H” active
“H” active
48
PE7
O
Not used (open)
49
BU-IN
I
Battery detect signal input from the SONY bus interface (IC501) and battery detect circuit
“L” is input at low voltage
“L” is input at low voltage
50
LINK-OFF
O
Link on/off control signal output for the SONY bus “L”: link on, “H”: link off
51
PD2
O
Not used (open)
52
ILL-ON
O
Power on/off control signal output of the illumination LED “H”: power on
Output select control signal output to the BA3834F (IC102) *1
*1 Output select logic table
GND
GND
68Hz
170Hz
420Hz
1kHz
2.4kHz
5.9kHz 14.4kHz
SPE-A (pin r; )
×
0
0
0
0
1
1
1
1
SPE-B (pin ra )
×
0
0
1
1
0
0
1
1
SPE-C (pin rs )
×
0
1
0
1
0
1
0
1
SPE-SEL (pin rd )
0
1
1
1
1
1
1
1
1
“
×
” is don't care
IC102 (pin qj )
AOUT
Terminal
49
Pin No.
Pin Name
I/O
Description
53
VSS
—
Ground terminal
54, 55
NC
O
Not used (open)
56
PD6
O
Not used (open)
57
BOOT
I
Serial data input at the flash memory writing mode “L” is input when writing change
58
VCC
—
Power supply terminal (+5V)
59
NC
O
Not used (open)
60
TX/LCD-DATA
O
Display serial data output to the liquid crystal display driver (IC901, 902)
Output terminal for UART transfer data when writing into internal flash memory data
Output terminal for UART transfer data when writing into internal flash memory data
61
SP-SI
I
Spectrum analyzer display serial data input terminal Not used (fixed at “L”)
62
RX
I
Input terminal for UART transfer data when writing into internal flash memory data
63
SP-SCK
I
Spectrum analyzer display serial data transfer clock signal input terminal
Not used (fixed at “L”)
Not used (fixed at “L”)
64
LCD-SCK
O
Display serial data transfer clock signal output to the liquid crystal display driver (IC901, 902)
65
VSS
—
Ground terminal
66
LCDCE0
O
Chip enable signal output to the liquid crystal display driver (IC901) “H” active
67, 68
VSS
—
Ground terminal
69
LCD-INH
O
Blank indicate control signal output to the liquid crystal display driver (IC901, 902)
“L”: no display
“L”: no display
70
LCDCE1
O
Chip enable signal output to the liquid crystal display driver (IC902) “H” active
71
NC
O
Not used (open)
72 to 78
P27 to P21
O
Not used (open)
79
FL W
O
Flash memory data write control signal output terminal “H”: active
80
FWE
I
Flash memory data write enable signal input terminal
81
RES
I
System reset signal input from the reset signal generator (IC602) and reset switch (S901, 902)
“L” is input for several 100 msec after power on, then it changes to “H”
“L” is input for several 100 msec after power on, then it changes to “H”
82
NMI
I
Non maskable interrupt input terminal
Connect the backup detect circuit (BU-IN pin rl) in this set
Connect the backup detect circuit (BU-IN pin rl) in this set
83
STBY
I
Hard ware standby input terminal Not used (pull down)
84
VCC
—
Power supply terminal (+5V)
85
XTAL
O
System clock output terminal (18.432 MHz)
86
EXTAL
I
System clock input terminal (18.432 MHz)
87
VSS
—
Ground terminal
88
PF7
O
Not used (open)
89
VCC
—
Power supply terminal (+5V)
90 to 96
PF6 to PF0
O
Not used (open)
97
UNI-SO
O
Serial data output to the SONY bus interface (IC501)
98
UNI-SI
I
Serial data input from the SONY bus interface (IC501)
99, 100
VSS
—
Ground terminal
101
UNICKI
I
Serial clock signal input from the system controller (IC601)
102
P53/ADTRG
O
Not used (open)
103
AVCC
—
Power supply terminal (+5V) (for A/D converter)
104
VREF
I
Reference voltage (+5V) input terminal (for A/D converter)
105
SPE-IN
I
Peak hold voltage detect signal input from the BA3834F (IC102)
106 to 110
P41/AN1 to
P45/AN5
I
Not used (fixed at “L”)
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