DOWNLOAD Sony XR-C5090 Service Manual ↓ Size: 3.34 MB | Pages: 31 in PDF or view online for FREE

Model
XR-C5090
Pages
31
Size
3.34 MB
Type
PDF
Document
Service Manual
Brand
Device
Car Audio
File
xr-c5090.pdf
Date
PREV: Sony MDX-C7890R (serv.man2) Service Manual

Sony XR-C5090 Service Manual ▷ View online

– 17 –
Pin No.
Pin Name
I/O
Function
70
UNISI
I
Serial data input from the bus interface (IC581) (for SONY bus)
71
UNICKO
O
Serial data transfer clock signal output to the bus interface (IC581) (for SONY bus)
72
BUSON
O
Bus on/off control signal output to the bus interface (IC581) (for SONY bus)    “L”: bus on
73
SYSRST
O
Reset signal output to the bus interface (IC581) (for SONY bus)    “L”: reset
74
VREG
O
CPU regulator output terminal    Connected to capacitor
75
GND
—
Ground terminal
76
X OUT
O
Main system clock output terminal (4.5 MHz)
77
X IN
I
Main system clock input terminal (4.5 MHz)
78
CE
I
CPU chip enable signal input (fixed at “H”)
79
VDD1
—
Power supply terminal (+5V)
80
RESET
I
System reset signal input from the reset signal generator (IC551) and reset switch (S551)
“L” is input for several 100 msec after power on, then it changes to “H”
*1  loading/tape operation motor control
                           MODE
 TERMINAL
LM LOD (pin 8)
“L”
“H”
“L”
“H”
LM EJ (pin 9)
“L”
“L”
“H”
“H”
STOP
LOADING/
FORWARD
EJECT/
REVERSE
BRAKE
– 19 –
– 20 –
6-2.
PRINTED  WIRING  BOARD  – MAIN Section –
– 24 –
3.4 Vp-p
221 ns
• Waveform
1
IC501 
&¶
 (X_IN)
– 29 –
• IC Block Diagrams – MAIN Board –
IC301
CXA2509AQ-T4
IC331
LC75373ED
+
–
+
–
+
–
+
–
+ –
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
21
22
23
26
27
28
29
30
31
32
33
34
37
38
39
40
24
25
PBFB2
PBRIN2
PBREF2
PBFIN2
35
36
PBGND
VCT
PBFIN1
PBREF1
PBRIN1
PBFB1
PBEQ1
PBOUT1
VCC
TAPEIN1
AUXIN1
MSLPF
LINEOUT1
NC
NC
G2FB
G1FB
MSTC
DGND
MSOUT
NC
NC
INSW
TAPESW
MSMODE
DRSW
MSSW
NC
NC
LINEOUT2
DIREF
AUXIN2
TAPEIN2
PBEQ2
PBOUT2
GND
F2
120
µ
/70
µ
X1
X1
VCT
+
F1
120
µ
/70
µ
24dB
OFF/B
F3
LPF
VCC
DETECT
MS ON/
OFF
FWD/RVS
TAPE EQ
TAPE/AUX
NR BIAS
24dB
MS
MODE
T2
T1
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
DECODER
LATCH
SHIFT
REGISTER
CONTROL
–
+
+ 
–
1
2
3 4
5
6 7 8
9 10
20
19
18
17
16
15
14
13
12
11
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
LSELO
L4
L3
L2
L1
VDD
R1
R2
R3
R4
RSELO
RVRIN
RCOM
RT1
RT2
RT3
RTOUT
RSIN
RS1
RS2
RS3
RSOUT
RFIN
RFOUT
RROUT
VSS
CL
DI
CE
VREF
LROUT
LFOUT
LFIN
LSOUT
LS3
LS2
LS1
LSIN
LTOUT
LT3
LT2
LT1
LCOM
LVRIN
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