DOWNLOAD Sony XES-Z50 (serv.man3) Service Manual ↓ Size: 13.79 MB | Pages: 127 in PDF or view online for FREE

Model
XES-Z50 (serv.man3)
Pages
127
Size
13.79 MB
Type
PDF
Document
Service Manual
Brand
Device
Car Audio
File
xes-z50-sm3.pdf
Date
PREV: Sony XES-Z50 (serv.man2) Service Manual

Sony XES-Z50 (serv.man3) Service Manual ▷ View online

– 165 –
IC502
SN74HC74ANS
14
1
2 3
4
5
6
7
13 12 11
10
9
8
VCC
GND
CK
CLR
CK
CLR
Q
PR
Q
Q
PR
Q
D
D
IC503
TC9246F-TP1
1
2
3
4
5
6
7
8
XO
XI
VSSA
A
MPO
AMPI
VDDA
PD
REF
16
15
14
13
12
11
10
9
VSS
CKO
M1
M2
S1
S2
LOCK
VDD
LOCK
DETECTION
CIRCUIT
MICRO COMPUTER
INTERFACE
PROGRAMMABLE COUNTER
VCO
PHASE
COMPARATOR
SELECTOR
REF.
VAR.
IC601
CXD2501Q
NOISE SHAPER
AND
PWM
MODULATOR
MIRR/
DFCT/
FOK
DETECTOR
JUMP/
SEARCH
CONTROL
A/D
CONVERTER
MPX
DSP
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
21 22 23 24 25 26 27 28 29 30 31 32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
56 55 54 53 52
51
50
49
48
47
57
58
59
60
61
62
63
64
µ
-COM INTERFACE
AD11
AD10
RF
TE
SE
NC
FE
VC
DVSS
NC
ATSK
NC
DFSW
DFCT
XTAL
NC
XTSL
LOCK
FOK
MIRR
CLK
NC
XLT
DATA
COUT
NC
DVDD
NC
SENS
SCLK
NC
DIRC
XRST
SOCK
XOLT
SOUT
NC
SFDR
SRON
SRDR
SFON
NC
DVSS
NC
TEST
NC
TFDR
TRON
TRDR
TFON
FFDR
FRON
FRDR
FFON
NC
SSTP
NC
CDS
AVSS
NC
IGEN
AVDD
DVDD
NC
IC951
MM1284XFFE
RESET
SW
SW
SW
1
2
3
4
5
6
7
8
9
10
14
13
12
11
VCC
BUS ON
LINK OFF
CLK OUT
DATA OUT
DATA IN
RESET
BUS RESET
BUS DATA
VREF
BUS CLK
GND
BUS ON INPUT
BUS ON OUT
IC801
BA6287F
– SW Board –
1
2
3
4
OUT1
VM
VCC
FIN
8
7
6
5
GND
OUT2
VREF
RIN
CONTROL LOGIC
TSD
POWER
SAVE
DRIVER
DRIVER
– 166 –
IC102, 202
HM51W4260CLTT-7
– DSP Board –
256K MEMORY
ARRAY MAT
ROW
DECODER
256K MEMORY
ARRAY MAT
ROW
DECODER
PERIPHERAL
CIRCUIT
1
2 3 4 5 6 7 8 9 10
20
19
18
17
16
15
14
13
12
11
21 22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
ADDRESS BUS
ADDRESS BUS
I/O BUS
I/O BUFFER
SELECTOR
SELECTOR
I/O BUFFER
I/O BUS
I/O BUS AND
COLUMN DECODER
I/O BUS AND
COLUMN DECODER
VSS
I/O15
I/O14
I/O13
I/O12
VSS
I/O11
I/O10
I/O9
I/O8
NC
NC
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
VSS
VCC
A3
A2
A1
A0
NC
RAS
WE
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
VCC
I/O3
I/O2
I/O1
I/O0
VCC
START/
STOP
LOGIC
DATA WORD
ADDRESS/
COUNTER
X
DECODER
DEVICE
ADDRESS
COMPARATOR
LOAD
COMP
SERIAL
CONTROL
LOGIC
DATA
RECOVERY
H.V.
PUMP/
TIMING
D OUT/
ACK
LOGIC
Y
DECODER
EEPROM
SERIAL
MUX
1
2
3
4
5
6
7
8
D OUT
D IN
R/W
LOAD
INC
EN
A0
A1
A2
VSS
VCC
WP
SCL
SDA
IC302
AT24C32N-10SI-TR
IC306
MM1284XFFE
RESET
SW
SW
SW
1
2
3
4
5
6
7
8
9
10
14
13
12
11
VCC
BUS ON
LINK OFF
CLK OUT
DATA OUT
DATA IN
RESET
BUS RESET
BUS DATA
VREF
BUS CLK
GND
BUS ON INPUT
BUS ON OUT
CONTROL
CIRCUIT
LOW VCC
DETECTOR CIRCUIT
WRITE/ERASE
PULSE TIMER
ERASE CIRCUIT
CHIP ENABLE/
OUTPUT ENABLE
CIRCUIT
I/O
BUFFER
DATA
LATCH
ADDRESS
LATCH
Y
DECODER
16,777,216
CELL
MATRIX
Y GATE
WRITE CIRCUIT
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
VSS
VSS
VCC
DQ4
DQ5
DQ6
DQ7
WE
OE
RY/BY
DQ3
DQ2
DQ1
DQ0
A0
A1
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
21
22
A14
A15
A19
A18
A17
NC
A11
CE
A8
A7
A5
A6
A13
VCC
RESET
A12
47
48
45
46
A4
NC
NC
A9
A16
A10
X
DECODER
NC
NC
A20
NC
NC
STB
STB
NC
NC
A2
A3
IC401
MBM29F016-90PFTN-DSP02L
IC402
MBM29F016-90PFTN-DSP02H
– 167 –
IC415
TC74VHC595FS (EL)
1
2
3
4
5
6
7
8
9
10
16
15
14
13
12
11
SHIFT REGISTER
LATCH
PARALLEL DATA
OUTPUT
GND
VCC
LATCH
CLOCK
PARALLEL DATA
OUTPUT
SERIAL DATA
INPUT
OUTPUT
ENABLE
SHIFT
CLOCK
SERIAL DATA
OUTPUT
RESET
QB
QC
QD
QE
QF
QG
QH
SQH
A
QA
IC502
CS8412-IS-E1
MULTIPLEXER
FREQUENCY
COMPARATOR
ERROR ENCODER
CHANNEL
STATUS LATCH
CRC
CHECK
CLOCK AND
DATA RECOVERY
CONFIDENCE
FLAG
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
21
22
23
24
25
26
27
28
PARITY
CHECK
TIMING
BI-PHASE
DECODER AND
FRAME SYNC
DE-
MULTIPLEXER
AUDIO
SERIAL
PORT
REGISTERS
6
3
3
6
VERF
CE/F2
SDATA
ERF
M1
M0
VA+
AGND
FILT
MCK
M2
M3
SEL
CBL
U
CS12/FCK
SCK
FSYNC
RXN
RXP
DGND
VD+
C0/E0
CA/E1
CB/E2
CC/F0
CD/F1
C
– 168 –
IC1101, 1201, 1301
SM5843AS1-ET
– DAC Board –
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
21
22
23
24
25
26
27
28
DI/NF2N
BCKI
CKSLN
INFIN
IWIN/DIL
XTI
XTO
VSS
CKO
IW2N/DIR
MDT
MCK
MLEN
RSTN
MUTE
DEMP
FSEL1
FSEL2
OW2ON
SYNCN
TMOD1
VDD
DOR
DOL
WCKO
BCKO
TMOD2
LRCI
OUTPUT DATE
INTERFACE
TIMING CONTROL
OP ATTENUATION
BLOCK
DE-EMPHASIS
CONTROL
MUTE/ATTENUATOR
CONTROL
SYSTEM CLOCK
INPUT DATA
INTERFACE
IC1102, 1103, 1202
PCM1702U-K-T1
IC1203, 1302, 1303
BALANCED
CURRENT
SEGMENT
DAC A
BALANCED
CURRENT
SEGMENT
DAC B
BIPOLAR
OFFSET
1
2
3
4
5
6
8
9
10
20
19
18
17
16
15
14
13
12
11
–VCC
REF DC
NC
SERVO DC
A.COM
A.COM
I OUT
NC
BPO DC
+VCC
NC
NC
NC
L.E
7
–VDD
D.COM
+VDD
NC
CLOCK
DATA
INPUT
INTERFACE
AND
SINE
CONVERTER
REFERENCE
AND
SERVO
IC1106, 1206, 1306
CS3310-KP
+
–
+ 
–
MUX
MUX
1
2
3
4
5
6
7
8
9
10
16
15
14
13
12
11
AINL
AGNDL
AOUTL
VA–
VA+
AOUTR
AGNDR
AINR
8
8
8
8
8
16
ZCEN
CS
SDATAI
VD+
DGND
SCLK
SDATAO
MUTE
CONTROL
REGISTER
SERIAL
PARALLEL
REGISTER
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