Sony XAV-7W (serv.man2) Service Manual ▷ View online
49
XAV-7W
REFERENCE
VOLTAGE
LATCH
TRIANGLE
OSCILLATOR
VERF.
+2.5V
+2.5V
+2.5V
+
–
U.V.L.O
–
+
+
+
–
–
1
2
3
4
5
6
7
8
9
10
16
15
14
13
12
11
PWM
COMPA-
RATOR2
RATOR2
OUTPUT2
OUTPUT1
GND
PWM
COMPA-
RATOR1
RATOR1
VERF
S
R
R
VERF
VERF
ERROR
AMP2
ERROR
AMP1
VREF/2
SHORT
CIRCUIT
PROTECTION
COMPARATOR
VCC
+
REF
OUT
S.C.P
NON-INV-
INPUT2
INV-
INPUT2
FEED
BACK2
DEAD
TIME
CONTROL2
OUT2
VCC
GND
OUT1
RT
NON-INV-
INPUT1
INV-
INPUT1
FEED
BACK1
DEAD
TIME
CONTROL1
CT
IC751
BA8270F-E2
IC860
TL1451ACDB
1
2
3
4
5
5
6
7
8
9
10
14
13
12
11
BUS ON
SWITCH
RESET
SWITCH
BATTERY
SWITCH
BUS ON
RST
BATT
CLK
VREF
DATA
GND
VCC
RST
BUS ON
BUS ON
CLK IN
BU IN
DATA IN
DATA OUT
IC50
SAA6588T/V2-118
SCOUT
MRO
MPTH
TCON
OSCO
OSCI
VSSD
VDDD
DAVN
SDA
VREF
MPX
VSSA
VDDA
AFIN
MAD
PSWN
SCL
2
1
6
15
11
13
16
14
12
INTERFACE
REGISTER
SIGNAL QUALITY
DECODER
CLOCKED
COMPARATOR
POWER SUPPLY
& RESET
TEST
CONTROL
OSCILLATOR
& CLOCK
PAUSE
DETECTOR
MULTI
PATH
DETECTOR
57kHz
8th ORDER
BAND-PASS FILTER
RDS/RDBS
DECODER
RDS/RDBS
DEMODULATOR
IIC BUS SLAVE
TRANSCEIVER
17
18
CIN
19
LVIN
20
8
7
DATA
CLOCK
DATA
CLOCK
4
4
5
9
10
3
4
5
50
XAV-7W
38
39 40 41 42 43
44
45
47
46
48
37
36
35
34
33
32
31
30
29
25
24 23 22
21
20
19
18 17
15
16
14
13
26
27
28
SYNC SEP
BGP GEN
WINDOW
PULSE GEN
γ
AMP
REG1
REG3
REG2
IDENT
KILLER
TRAP
AGC
HPF
COLOR
CLAMP
AGC AMP
AGC DET
AGC DET
PICTURE
INV
5
7
8
9
10
11
12
6
3
1
2
4
F/F
PAL SW
TINT
VCO
APC
PHASE
SHIFT
P
N
COMP
COMP
MATRIX
INT/EXT SW
γ
AMP
γ
AMP
INV
INV
VREF
DEMOD
R-Y G-Y B-Y
SYNC
IN
Y/C
Y/C
BGP
F/F
Y
R-Y
G-Y
B-Y
PAL
ON
P
N
N
P
CHROMA OUT
ACC FILTER
B-Y
R-Y
KILLER FILTER
BURST OUT
COLOR
COLOR
C IN
IDENT FILTER
VIDEO IN
CONTRAST
TRAP
PICTURE
AGC OUT
AGC FILTER
CLAMP
F ADJ
VCC1
G IN
R IN
B IN
SW
COMMON OUT
COMMON
AMPLITUDE
ADJUST
SYNC SEP
SYNC OUT
SYNC IN
FRP
SUB BRIGHT R
SUB BRIGHT B
BRIGHT
GAMMA 0
GAMMA 2
B DC DET
RGB AMPLITUED
ADJUST
COMMON
FRP
B OUT
VCC2
G DC DET
G OUT
R DC DET
R OUT
GND2
GND1
VCO OUT
APC FILTER
VCO IN
TINT
P
N P
N
– MONITOR Board –
IC201
IR3Y29B4
51
XAV-7W
DRIVER
DRIVER
NC
NC
NC
GND
OUT2
RNF
FIN
VCC
OUT1
5
6
16
VM
15
NC
14
NC
13
17
POWER SAVE
18
RIN
19
VREF
20
7 8
CONTROL
LOGIC
POWER
SAVE
TSD
24 – 21
1 – 4
9 – 12
– MOTOR Board –
IC702
BA6285FP-E2
A
B
GND
VCC
RX/CX
CX
Q
CX
Q
5
6
1
2
3
4
7
8
CLR
CLR
Cx
Rx/Cx
Q
IC900
MB3785APFV-G-BND-ER
CB 4
VE 4
OUT 3
VE 3
VE 2
OUT 2
OUT 1
VE 1
GND
V
CC
2
OUT 4
CB 1
40
42
43
44
48
3
37
38
39
41
RE
D
RE
C
45
46
47
RE
B
RE
A
36 35 34 33 32
31 30
29
28 27
26 25
CA 4
CB 3
CA 3
DTC 4
FB 4
–
IN 4 (E)
+IN 4 (E)
–
IN 3 (E)
+IN 3 (E)
DTC 3
FB 3
–
IN 4 (C)
D
C
24
23
4
5
2
1
SAW
OSC
CT
RT
RT
XTAL
XTAL
–IN 2 (C)
V
CC
1
VOLTAGE
REFERENCE
+2.5V
22
21
20
–IN 3 (C)
SCP
CTL 3
CTL 2
CTL 1
VREF
CT
RT
OSCO
RT
OSCO
OSCI
19
18
17
16
15
14
13
B
A
6
7
8
9 10
11 12
–
IN 1 (C)
CA 2
DTC 1
FB 1
DTC 2
FB 2
–
IN 2 (E)
+IN 2 (E)
–
IN 1 (E)
+IN 1 (E)
CB 2
CA 1
A
B
C
D
IC250
TC7WH123FU (TE12R)
52
XAV-7W
6-26.
IC PIN FUNCTION DESCRIPTION
•
MAIN BOARD IC2 MB90096PF-G-238-BND-ER (ON SCREEN DISPLAY CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
CPOUT
O
Horizontal period phase comparison result signal output terminal Not used
2
AVSS
—
Ground terminal (for internal VCO)
3
VCOIN
I
Internal VCO voltage input terminal Not used
4
AVSS
—
Ground terminal (for internal VCO)
5
RESET
I
Reset signal input from the display controller “L”: reset
6
TEST
I
Input terminal for the test
7
VSS
—
Ground terminal
8
DOCKI
I
Dot clock signal input terminal Horizontal sync signal input in this set
9
DOCKO
O
Dot clock signal output terminal Not used
10
FH
O
Output terminal of horizontal period signal generated in PLL circuit Not used
11
EVEN
I
Field control signal input terminal Not used
12
HSYNC
I
Horizontal sync signal input from the liquid crystal display driver (for monitor)
Based in this signal period, dot clock signal is generated Active level is programmable
Based in this signal period, dot clock signal is generated Active level is programmable
13
VSYNC
I
Vertical sync signal input from the liquid crystal display driver (for monitor)
Active level is programmable
Active level is programmable
14
DISP
I
Video muting on/off control signal input from the master controller “L”: muting on
15
VOB2
O
Semi-transparent period output terminal Active level is programmable Not used
16
VOB1
O
OSD display period output terminal Active level is programmable
17
IOUT
O
Color signal (I) output terminal Active level is programmable
18
GOUT
O
Color signal (G) output terminal Active level is programmable
19
ROUT
O
Color signal (R) output terminal Active level is programmable
20
BOUT
O
Color signal (B) output terminal Active level is programmable
21
V3V
—
Coupling capacitor connection terminal
22
VCC
—
Power supply terminal (+5V)
23
TRE
O
Output of signal indicating that the command is being transferred to display controller and the fill
operation is under way “H” active
operation is under way “H” active
24
SCLK
I
Serial data transfer clock signal input from the display controller
25
SIN
I
Serial data input from the display controller
26
CS
I
Chip select signal input from the display controller “L” active
27
AVCC
—
Power supply terminal (+5V) (for internal VCO)
28
AV3V
—
Coupling capacitor connection terminal
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