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Model
MEX-GS610BE MEX-GS610BT MEX-N6050BT
Pages
59
Size
8.13 MB
Type
PDF
Document
Service Manual
Brand
Device
Car Audio
File
mex-gs610be-mex-gs610bt-mex-n6050bt.pdf
Date

Sony MEX-GS610BE / MEX-GS610BT / MEX-N6050BT Service Manual ▷ View online

MEX-GS610BE/GS610BT/N6050BT
41
•  IC Pin Function Description
MAIN  BOARD  IC503  R7S7200022CFP (SYSTEM  CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
BT_MIC_DET
I
External microphone plug insert detection signal input terminal for the Bluetooth
2
AMP_ATT
O
Amplifi er muting on/off control signal output to the power amplifi er    “L”: muting on
3
AMPSTB
O
Standby signal output to the power amplifi er    “L”: standby
4
SERVO_ON
O
Power on/off control signal output to the servo section    “H”: power on
5
SP_CLK
O
Serial data transfer clock signal output to the audio DSP
6
SP_DATA
I
Serial data input from the audio DSP
7
Vcc
-
Power supply terminal (+1.18V) (for internal)
8
DEC_XMUTE
O
Muting on/off control signal output to the audio DSP    “L”: muting on
9
Vss
-
Ground terminal
10
CD_ZDET
I
Zero data detection signal input from the audio DSP
11
PVcc
-
Power supply terminal (+3.3V) (for I/O)
12
BSIF_GATE
O
Gate signal output to the audio DSP
13
DEC_INT
I
Interrupt signal input from the audio DSP
14
DSP_RST
O
Reset signal output to the audio DSP    “L”: reset
15
DSP_SSTBY
O
Standby signal output to the audio DSP    “L”: standby
16
BSIF_ST_REQ
I
Request signal input from the audio DSP
17
CD_BUSCLK
O
Serial data transfer clock signal output to the audio DSP
18
Vss
-
Ground terminal
19
CD_XCCE
O
Chip enable signal output to the audio DSP
20
CD_SDO
O
Serial data output to the audio DSP
21
Vcc
-
Power supply terminal (+1.18V) (for internal)
22
CD_SDI
I
Serial data input from the audio DSP
23
Vss
-
Ground terminal
24
BSIF_BCK
O
Bit clock signal output to the audio DSP
25
PVcc
-
Power supply terminal (+3.3V) (for I/O)
26
BSIF_LR
O
L/R sampling clock signal output to the audio DSP
27
BSIF_DO
O
Audio data output to the audio DSP
28
BEEP
O
Beep sound drive signal output to the power amplifi er
29
DEC_BCK_IN
I
Bit clock signal input from the audio DSP
30
DEC_LRCK_IN
I
L/R sampling clock signal input from the audio DSP
31
Vss
-
Ground terminal
32
DEC_SDOUT_F
O
Audio data output to the audio DSP
33
DEC_SDIN_CH0
I
Audio data input from the audio DSP
34
Vcc
-
Power supply terminal (+1.18V) (for internal)
35
LCD_CLK
O
Serial data transfer clock signal output to the front panel block
36
Vss
-
Ground terminal
37
NC
-
Not used
38
LCD_CE
O
Chip enable signal output to the front panel block
39
PVcc
-
Power supply terminal (+3.3V) (for I/O)
40
LCD_DO
O
Serial data output to the front panel block
41
MEC_EJECT
O
Loading motor drive signal (eject direction) output terminal    “H”: motor on
42
SYNC_OUT
O
Frequency control signal output to the regulator and DC/DC converter
43
DEBUG_TX
O
Transmit data output terminal for the debug    Not used
44
LRCK_INT
I
L/R sampling clock signal input from the pin 26 (BSIF_LR)
45
ACC_IN
I
Accessory power detection signal input terminal    “L”: accessory power on
46
Vss
-
Ground terminal
47
DRV_ON
O
Driver control signal output to the CD mechanism deck block
48
XM_TX
O
Serial data output to the SIRIUSXM in connector (MEX-GS610BT only)
49
KEY_ACK1
I
Key acknowledge signal (wake up signal) input from the front panel block
50
PVcc
-
Power supply terminal (+3.3V) (for I/O)
51
MEC_INSW
I
Disc insert detection switch input terminal
52
BT_CLK
I
Serial data transfer clock signal input from the BT module
53
BT_SYNC
I
Sync signal input from the BT module
54
BT_DOUT
O
Audio data output to the BT module
55
BT_DIN
I
Audio data input from the BT module
56
BU_IN
I
Back-up power detection signal input terminal    “L” is input at low voltage
MEX-GS610BE/GS610BT/N6050BT
42
Pin No.
Pin Name
I/O
Description
57
MEC_LIMIT
I
Limit in detection switch input terminal
58
Vcc
-
Power supply terminal (+1.18V) (for internal)
59
KEY_ACK0
I
Key acknowledge signal (wake up signal) input from the rotary commander
60
MEC_LOAD
O
Loading motor drive signal (loading direction) output terminal    “H”: motor on
61
Vss
-
Ground terminal
62
PVcc
-
Power supply terminal (+3.3V) (for I/O)
63
XM_RX
I
Serial data input from the SIRIUSXM in connector (MEX-GS610BT only)
64
DEBUG_RX
I
Receive data input terminal for the debug    Not used
65
BT_RX
I
Serial data input from the BT module
66
TBD
I
Fixed at “L” in this unit
67
RTC_X1
I
System clock input terminal (32.768 kHz)
68
RTC_X2
O
System clock output terminal (32.768 kHz)
69
PLLVcc
-
Power supply terminal (+1.18V) (for PLL)
70
EXTAL
I
System clock input terminal (13.333 MHz)
71
XTAL
O
System clock output terminal (13.333 MHz)
72, 73
Vss
-
Ground terminal
74
NMI
I
Fixed at “H” in this unit
75
Vss
-
Ground terminal
76
RES
I
System reset signal input from the reset signal generator    “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
77
PVcc
-
Power supply terminal (+3.3V) (for I/O)
78 to 80
NC
-
Not used
81
RC_IN0
I
Rotary commander key input terminal
82, 83
KEY_IN0, KEY_IN1
I
Front panel key input terminal
84, 85
NC
-
Not used
86
AVcc
-
Power supply terminal (+3.3V) (analog system)
87
Vss
-
Ground terminal
88
AVref
-
Reference power supply (+3.3V) input terminal (analog system)
89
BSCANP
I
Fixed at “L” in this unit
90
PVcc
-
Power supply terminal (+3.3V) (for I/O)
91
AUDIO_X1
I
Audio clock signal input terminal
92
NC
-
Not used
93
Vss
-
Ground terminal
94
SYNC_ON
O
Not used
95
Vcc
-
Power supply terminal (+1.18V) (for internal)
96
XM_PWR
O
Power supply on/off control signal output to the SIRIUSXM in connector    “H”: power on 
(MEX-GS610BT only)
97
TRST
I
Reset signal input terminal for the JTAG    Not used
98
TDO
O
Data output terminal for the JTAG    Not used
99
TDI
I
Data input terminal for the JTAG    Not used
100
TMS
I
Mode selection signal input terminal for the JTAG    Not used
101
TCK
I
Clock signal input terminal for the JTAG    Not used
102
Vss
-
Ground terminal
103
ILL_IN
I
Illuminate line detection signal input terminal
104
EN_SYS
O
Power on/off control signal output to the regulator and DC/DC converter    “H”: power on
105
Vcc
-
Power supply terminal (+1.18V) (for internal)
106
PWR_ECO
O
Low power mode selection signal output to the regulator    “L”: low power mode
107
Vss
-
Ground terminal
108
USB_OVR
I
USB over current detection signal input from the regulator    “L”: over current
109
PVcc
-
Power supply terminal (+3.3V) (for I/O)
110
USB_ON2
O
USB power on/off control signal output to the DC/DC converter    “H”: power on
111
USB_OVR2
I
USB over current detection signal input from the DC/DC converter    “L”: over current
112
BT_PWR
O
Power on/off control signal output terminal for the Bluetooth section    “H”: power on
113
NC
-
Not used
114
BT_RST
O
Reset signal output to the BT module    “L”: reset
115
NC
-
Not used
116
Vss
-
Ground terminal
117
NC
-
Not used
118
USB_ON
O
USB power on/off control signal output to the regulator    “H”: power on
119
Vcc
-
Power supply terminal (+1.18V) (for internal)
MEX-GS610BE/GS610BT/N6050BT
43
Pin No.
Pin Name
I/O
Description
120
RC_IN1
I
Rotary commander shift key input terminal
121
Vss
-
Ground terminal
122
RE_ON
O
Jog dial pulse pull-up signal output terminal
123
PVcc
-
Power supply terminal (+3.3V) (for I/O)
124
MEC_DSW
I
Chucking end detection switch input terminal
125
I2C0_SCL
O
Serial data transfer clock signal output to the electrical volume, regulator and EEPROM
126
I2C0_SDA
I/O
Two-way data bus with the electrical volume, regulator and EEPROM
127
I2C1_SCL
O
Serial data transfer clock signal output to the tuner unit
128
I2C1_SDA
I/O
Two-way data bus with the tuner unit
129, 130
NC
-
Not used
131, 132
RE_IN0, RE_IN1
I
Jog dial pulse input from the rotary encoder
133
BT_TX
O
Serial data output to the BT module
134
USB_CHG_MOD2
O
USB charge control signal output terminal    Not used
135
DOOR_SW
I
Front panel remove/attach detection signal input terminal    “L”: Front panel is attached
136
SIRCS
I
Remote control signal input from the front panel block
137
MEC_SELFSW
I
Self loading position detection switch input terminal
138
Vss
-
Ground terminal
139
USB_X1
I
System clock input terminal (48 MHz)
140
USB_X2
O
System clock output terminal (48 MHz)
141
USBDPVcc
-
Power supply terminal (+3.3V) (for USB digital)
142
USBDPVss
-
Ground terminal (for USB digital)
143 to 
145
NC
-
Not used
146
USBDVcc
-
Power supply terminal (+1.18V) (for USB digital)
147
USBDVss
-
Ground terminal (for USB digital)
148
USBDPVcc
-
Power supply terminal (+3.3V) (for USB digital)
149
USBDPVss
-
Ground terminal (for USB digital)
150
DM0
I/O
Two-way USB data (–) bus with the USB controller
151
DP0
I/O
Two-way USB data (+) bus with the USB controller
152
VBUSIN0
I
VBUS power detection signal input terminal    “H”: VBUS power is detected
153
USBDVcc
-
Power supply terminal (+1.18V) (for USB digital)
154
USBDVss
-
Ground terminal (for USB digital)
155
REFRIN
I
External resistor connection terminal
156
USBAPVss
-
Ground terminal (for USB analog)
157
USBAPVcc
-
Power supply terminal (+3.3V) (for USB analog)
158
USBAVcc
-
Power supply terminal (+1.18V) (for USB analog)
159
USBAVss
-
Ground terminal (for USB analog)
160
USBUVcc
-
Power supply terminal (+1.18V) (for USB 48 MHz)
161
USBUVss
-
Ground terminal (for USB 48 MHz)
162, 163
Vss
-
Ground terminal
164, 165
NC
-
Not used
166
SF1_D2
O
Write protect signal output to the serial fl ash
167
SF1_D3
O
Hold signal output to the serial fl ash
168
SF1_CLK
O
Serial data transfer clock signal output to the serial fl ash
169
SF1_CE
O
Chip select signal output to the serial fl ash
170
SF1_D0
O
Serial data output to the serial fl ash
171
Vss
-
Ground terminal
172
SF1_D1
I
Serial data input from the serial fl ash
173
USB_CHG_MOD1
O
USB charge control signal output terminal    Not used
174
PVcc
-
Power supply terminal (+3.3V) (for I/O)
175
ATT
O
Audio muting on/off control signal output terminal    “H”: muting on
176
HIT2_RESET
O
Reset signal output to the tuner unit    “L”: reset
MEX-GS610BE/GS610BT/N6050BT
44
MAIN  BOARD  IC705  TC94A99FG-003 (SYCH (RF  AMP,  DIGITAL  SERVO  PROCESSOR,  AUDIO  DSP)
Pin No.
Pin Name
I/O
Description
1
LPFO
O
PLL circuit low-pass fi lter amplifi er output terminal
2
PVREF
-
PLL circuit reference voltage (+1.65V) terminal
3
VCOF
O
VCO fi lter terminal
4
RVSS3
-
Ground terminal
5
VCOI
I
DSP VCO control voltage input terminal
6
RVDD3
-
Power supply terminal (+3.3V)
7
SLCO
O
EFM slice level output terminal
8
RFI
I
RF signal input terminal
9
RFRPI
I
RF ripple signal input terminal
10
RFEQO
O
RF equalizer circuit output terminal
11
DCOFC
O
RF equalizer offset compensation low-pass fi lter output terminal
12
AGCI
I
RF signal auto gain control amplifi er input terminal
13
RFO
O
RF signal generation amplifi er output terminal
14
RVSS3
-
Ground terminal
15
FNI2
I
Main beam (B) input from the CD mechanism deck block
16, 17
FNI1, FPI2
I
Main beam (C) input from the CD mechanism deck block
18
FPI1
I
Main beam (A) input from the CD mechanism deck block
19
VDD1-1
-
Power supply terminal (+1.5V)
20
TPI
I
Sub beam (F) input from the CD mechanism deck block
21
TNI
I
Sub beam (E) input from the CD mechanism deck block
22
VRO
O
Reference voltage (+1.65V) output to the CD mechanism deck block
23
AVSS3
-
Ground terminal
24
MDI
I
Laser power detection signal input from the CD mechanism deck block
25
LDO
O
Laser power control signal output the CD mechanism deck block
26
FSMONIT
O
Not used
27
RFZI
I
RF ripple zero-cross signal input terminal
28
RFRP
O
RF ripple signal output terminal
29
TEI
O
Tracking error signal output terminal
30
AVDD3
-
Power supply terminal (+3.3V)
31
FOO
O
Focus coil control signal output to the CD mechanism deck block
32
TRO
O
Tracking coil control signal output to the CD mechanism deck block
33
VSS-1
-
Ground terminal
34
FMO
O
Sled motor control signal output to the CD mechanism deck block
35
DMO
O
Spindle motor control signal output to the CD mechanism deck block
36
VDDM1
-
Power supply terminal (+1.5V)
37
/SRAMSTB
I
Standby signal input from the system controller    “L”: standby
38
VDD1-2
-
Power supply terminal (+1.5V)
39
VDD3-1
-
Power supply terminal (+3.3V)
40, 41
PIO10, PIO11
I/O
Not used
42
SDIN_R
I
Audio data input from the system controller
43
BCK_IN_R
I
Bit clock signal input from the pin 49 (BCK_OUT)
44
LRCK_IN_R
I
L/R sampling clock signal input from the pin 48 (LRCK_OUT)
45
SDOUT_CH0
O
Audio data output to the system controller
46, 47
PIO16, PIO17
I/O
Not used
48
LRCK_OUT
O
L/R sampling clock signal output to the system controller
49
BCK_OUT
O
Bit clock signal output to the system controller
50
PIO20
I/O
Not used
51
DVDD12
-
Power supply terminal (+3.3V)
52
DAO1 (R_R-CH)
O
Audio signal (rear R-ch) output to the electrical volume
53
DVSS12
-
Ground terminal
54
DAO2 (F_R-CH)
O
Audio signal (front R-ch) output to the electrical volume
55
DVREF
-
Reference voltage terminal
56
DVDD34
-
Power supply terminal (+3.3V)
57
DAO3 (F_L-CH)
O
Audio signal (front L-ch) output to the electrical volume
58
DVSS34
-
Ground terminal
59
DAO4 (R_L-CH)
O
Audio signal (rear L-ch) output to the electrical volume
60
DVDD5
-
Power supply terminal (+3.3V)
61
DAO5 (SUB-CH)
O
Audio signal (sub-ch) output to the electrical volume
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