Sony MDX-C7900 / MDX-C7900R Service Manual ▷ View online
– 55 –
5-11.
IC PIN FUNCTION DESCRIPTION
•
SERVO BOARD IC301 CXD2652AR
Pin No.
Pin Name
I/O
Function
1
MNT0
O
Focus OK signal output to the MD mechanism controller (IC501)
“H” is output when focus is on (“L”: NG)
“H” is output when focus is on (“L”: NG)
2
MNT1
O
Track jump detection signal output to the MD mechanism controller (IC501)
3
MNT2
O
Monitor 2 signal output to the MD mechanism controller (IC501)
4
MNT3
O
Monitor 3 signal output to the MD mechanism controller (IC501)
5
SWDT
I
Writing serial data signal input from the MD mechanism controller (IC501)
6
SCLK
I
Serial data transfer clock signal input from the MD mechanism controller (IC501)
7
XLAT
I
Serial data latch pulse signal input from the MD mechanism controller (IC501)
8
SRDT
O (3)
Reading serial data signal output to the MD mechanism controller (IC501)
9
SENS
O (3)
Internal status (SENSE) output to the MD mechanism controller (IC501)
10
XRST
I
Reset signal input from the MD mechanism controller (IC501) “L”: reset
11
SQSY
O
Subcode Q sync (SCOR) output to the MD mechanism controller (IC501)
“L” is output every 13.3 msec Almost all, “H” is output
“L” is output every 13.3 msec Almost all, “H” is output
12
DQSY
O
Digital In U-bit CD format subcode Q sync (SCOR) output terminal
“L” is output every 13.3 msec Almost all, “H” is output Not used (open)
“L” is output every 13.3 msec Almost all, “H” is output Not used (open)
13
RECP
I
Laser power selection signal input terminal
“H”: recording mode, “L”: playback mode (fixed at “L” in this set)
“H”: recording mode, “L”: playback mode (fixed at “L” in this set)
14
XINT
O
Interrupt status output to the MD mechanism controller (IC501)
15
TX
I
Recording data output enable signal input terminal
Writing data transmission timing input (Also serves as the magnetic head on/off output)
Not used (fixed at “L”)
Writing data transmission timing input (Also serves as the magnetic head on/off output)
Not used (fixed at “L”)
16
OSCI
I
System clock signal (512Fs=22.5792 MHz) input from the oscillator circuit
17
OSCO
O
System clock signal (512Fs=22.5792 MHz) output terminal Not used (open)
18
XTSL
I
Input terminal for the system clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
19
RVDD
—
Power supply terminal (+3.3V) (digital system)
20
RVSS
—
Ground terminal (digital system)
21
DIN
I
Digital audio signal input terminal when recording mode (for optical in) Not used (fixed at “L”)
22
DOUT
O
Digital audio signal output terminal when playback mode (for optical out) Not used (open)
23
ADDT
I
Recording data input terminal Not used (fixed at “L”)
24
DADT
O
Playback data output terminal Not used (open)
25
LRCK
O
L/R sampling clock signal (44.1 kHz) output terminal Not used (open)
26
XBCK
O
Bit clock signal (2.8224 MHz) output terminal Not used (open)
27
FS256
O
Clock signal (11.2896 MHz) output to the PCM1717E (IC202)
28
DVDD
—
Power supply terminal (+3.3V) (digital system)
29
A03
O
30
A02
O
31
A01
O
32
A00
O
33
A10
O
Address signal output to the external D-RAM Not used (open)
34
A04
O
35
A05
O
36
A06
O
Address signal output to the D-RAM (IC307)
37
A07
O
38
A08
O
39
A11
O
Address signal output to the external D-RAM Not used (open)
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER, 2M BIT D-RAM)
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER, 2M BIT D-RAM)
Address signal output to the D-RAM (IC307)
– 56 –
Pin No.
Pin Name
I/O
Function
40
DVSS
—
Ground terminal (digital system)
41
XOE
O
Output enable signal output to the D-RAM (IC307) “L” active
42
XCAS
O
Column address strobe signal output to the D-RAM (IC307) “L” active
43
A09
O
Address signal output to the external D-RAM Not used (open)
44
XRAS
O
Row address strobe signal output to the D-RAM (IC307) “L” active
45
XWE
O
Write enable signal output to the D-RAM (IC307) “L” active
46
D1
I/O
47
D0
I/O
48
D2
I/O
49
D3
I/O
50
MVCI
I
Digital in PLL oscillation input from the external VCO Not used (fixed at “L”)
51
ASYO
O
Playback EFM full-swing output terminal
52
ASYI
I (A)
Playback EFM asymmetry comparator voltage input terminal
53
AVDD
—
Power supply terminal (+3.3V) (analog system)
54
BIAS
I (A)
Playback EFM asymmetry circuit constant current input terminal
55
RFI
I (A)
Playback EFM RF signal input from the CXA2523R (IC302)
56
AVSS
—
Ground terminal (analog system)
57
PDO
O (3)
Phase comparison output for clock playback analog PLL of the playback EFM Not used (open)
58
PCO
O (3)
Phase comparison output for master clock of the recording/playback EFM master PLL
59
FILI
I (A)
Filter input for master clock of the recording/playback master PLL
60
FILO
O (A)
Filter output for master clock of the recording/playback master PLL
61
CLTV
I (A)
Internal VCO control voltage input of the recording/playback master PLL
62
PEAK
I (A)
Light amount signal (RF/ABCD) peak hold input from the CXA2523R (IC302)
63
BOTM
I (A)
Light amount signal (RF/ABCD) bottom hold input from the CXA2523R (IC302)
64
ABCD
I (A)
Light amount signal (ABCD) input from the CXA2523R (IC302)
65
FE
I (A)
Focus error signal input from the CXA2523R (IC302)
66
AUX1
I (A)
Auxiliary signal (I
3
signal/temperature signal) input terminal Not used (fixed at “H”)
67
VC
I (A)
Middle point voltage (+1.65V) input from the CXA2523R (IC302)
68
ADIO
O (A)
Monitor output of the A/D converter input signal Not used (open)
69
AVDD
—
Power supply terminal (+3.3V) (analog system)
70
ADRT
I (A)
A/D converter operational range upper limit voltage input terminal (fixed at “H” in this set)
71
ADRB
I (A)
A/D converter operational range lower limit voltage input terminal (fixed at “L” in this set)
72
AVSS
—
Ground terminal (analog system)
73
SE
I (A)
Sled error signal input from the CXA2523R (IC302)
74
TE
I (A)
Tracking error signal input from the CXA2523R (IC302)
75
AUX2
I (A)
Auxiliary signal input terminal Light amount signal input from the CXA2523R (IC302)
76
DCHG
I (A)
Connected to the +3.3V power supply
77
APC
I (A)
Error signal input for the laser automatic power control Not used (fixed at “L”)
78
ADFG
I
ADIP duplex FM signal (22.05 kHz
±
1 kHz) input from the CXA2523R (IC302)
79
F0CNT
O
Filter f0 control signal output terminal Not used (open)
80
XLRF
O
Serial data latch pulse signal output terminal Not used (open)
81
CKRF
O
Serial data transfer clock signal output terminal Not used (open)
82
DTRF
O
Writing serial data output terminal Not used (open)
83
APCREF
O
Control signal output to the reference voltage generator circuit for the laser automatic power
control
control
84
LDDR
O
PWM signal output for the laser automatic power control Not used (open)
85
TRDR
O
Tracking servo drive PWM signal (–) output to the BH6511FS (IC303)
86
TFDR
O
Tracking servo drive PWM signal (+) output to the BH6511FS (IC303)
Two-way data bus with the D-RAM (IC307)
– 57 –
Pin No.
Pin Name
I/O
Function
87
DVDD
—
Power supply terminal (+3.3V) (digital system)
88
FFDR
O
Focus servo drive PWM signal (+) output to the BH6511FS (IC303)
89
FRDR
O
Focus servo drive PWM signal (–) output to the BH6511FS (IC303)
90
FS4
O
Clock signal (176.4 kHz) output terminal (X’tal system) Not used (open)
91
SRDR
O
Sled servo drive PWM signal (–) output to the BH6511FS (IC303)
92
SFDR
O
Sled servo drive PWM signal (+) output to the BH6511FS (IC303)
93
SPRD
O
Spindle servo drive PWM signal (–) output to the BH6511FS (IC303)
94
SPFD
O
Spindle servo drive PWM signal (+) output to the BH6511FS (IC303)
95
FGIN
I
Not used (fixed at “L”)
96
TEST1
I
97
TEST2
I
Input terminal for the test (fixed at “L”)
98
TEST3
I
99
DVSS
—
Ground terminal (digital system)
100
EFMO
O
EFM signal output terminal when recording mode Not used (open)
* I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
– 58 –
•
SERVO BOARD IC302 CXA2523R (RF AMP, FOCUS/TRACKING ERROR AMP)
Pin No.
Pin Name
I/O
Function
1
I
I
I-V converted RF signal I input from the optical pick-up block detector
2
J
I
I-V converted RF signal J input from the optical pick-up block detector
3
VC
O
Middle point voltage (+1.65V) generation output terminal
4 to 9
A to F
I
Signal input from the optical pick-up detector
10
PD
I
Light amount monitor input from the optical pick-up block laser diode
11
APC
O
Laser amplifier output terminal to the automatic power control circuit
12
APCREF
I
Reference voltage input terminal for setting laser power
13
GND
—
Ground terminal
14
TEMPI
I
Connected to the temperature sensor Not used (open)
15
TEMPR
O
Output terminal for a temperature sensor reference voltage Not used (open)
16
SWDT
I
Writing serial data input from the MD mechanism controller (IC501)
17
SCLK
I
Serial data transfer clock signal input from the MD mechanism controller (IC501)
18
XLAT
I
Serial data latch pulse signal input from the MD mechanism controller (IC501)
19
XSTBY
I
Standby signal input terminal “L”: standby (fixed at “H” in this set)
20
F0CNT
I
Center frequency control voltage input terminal of internal circuit (BPF22, BPF3T, EQ) input
terminal
terminal
21
VREF
O
Reference voltage output terminal Not used (open)
22
EQADJ
I
Center frequency setting terminal for the internal circuit (EQ)
23
3TADJ
I
Center frequency setting terminal for the internal circuit (BPF3T)
24
VCC
—
Power supply terminal (+3.3V)
25
WBLADJ
I
Center frequency setting terminal for the internal circuit (BPF22)
26
TE
O
Tracking error signal output to the CXD2652AR (IC301)
27
CSLED
I
Connected to the external capacitor for low-pass filter of the sled error signal
28
SE
O
Sled error signal output to the CXD2652AR (IC301)
29
ADFM
O
FM signal output of the ADIP
30
ADIN
I
Receives a ADIP FM signal in AC coupling
31
ADAGC
I
Connected to the external capacitor for ADIP AGC
32
ADFG
O
ADIP duplex signal (22.05 kHz
±
1 kHz) output to the CXD2652AR (IC301)
33
AUX
O
Auxiliary signal (I
3
signal/temperature signal) output terminal Not used (open)
34
FE
O
Focus error signal output to the CXD2652AR (IC301)
35
ABCD
O
Light amount signal (ABCD) output to the CXD2652AR (IC301)
36
BOTM
O
Light amount signal (RF/ABCD) bottom hold output to the CXD2652AR (IC301)
37
PEAK
O
Light amount signal (RF/ABCD) peak hold output to the CXD2652AR (IC301)
38
RF
O
Playback EFM RF signal output to the CXD2652AR (IC301)
39
RFAGC
I
Connected to the external capacitor for RF auto gain control circuit
40
AGCI
I
Receives a RF signal in AC coupling
41
COMPO
O
User comparator output terminal Not used (open)
42
COMPP
I
User comparator input terminal Not used (fixed at “L”)
43
ADDC
I
Connected to the external capacitor for cutting the low band of the ADIP amplifier
44
OPO
O
User operational amplifier output terminal Not used (open)
45
OPN
I
User operational amplifier inversion input terminal Not used (fixed at “L”)
46
RFO
O
RF signal output terminal
47
MORFI
I
Receives a MO RF signal in AC coupling
48
MORFO
O
MO RF signal output terminal
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