Sony MDX-C6400R / MDX-C6500R / MDX-C6500RX Service Manual ▷ View online
37
IC303
BH6511FS-E2
IC305
BA6287F
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
VG
IN4R
IN4F
VM4
OUT4F
PGND4
OUT4R
VM34
OUT3R
PGND3
OUT3F
VM3
IN3F
IN3R
PSB
CAPA–
CAPA+
IN2R
IN2F
VM2
OUT2F
PGND2
OUT2R
VM12
OUT1R
PGND1
OUT1F
VM1
IN1F
IN1R
V
DD
CHARGE
PUMP.
OSC
INTERFACE
AMP
INTERFACE
AMP
AMP
INTERFACE
PREDRIVE
PREDRIVE
PREDRIVE
PREDRIVE
AMP
INTERFACE
AMP
AMP
AMP
V
DD
PSB
AMP
1
2
3
4
OUT1
VM
VCC
FIN
8
7
6
5
GND
OUT2
VREF
RIN
CONTROL LOGIC
TSD
POWER
SAVE
DRIVER
DRIVER
IC307
MN41V4400TT-08S
DATA BUS
DQ3
DQ4
VSS
3
DQ2
2
A9
5
A0
9
A1
10
A2 11
A3 12
A3 12
VCC 13
NC
6
NC
7
NC
8
DQ1
1
26
23
24
25
A8
NC
NC
NC
NC
19
20
21
A6
A7
17
18
A4
A5
15
14
16
ROW
DECODERS
WORD
DRIVERS
MEMORY
CELLS
INTERNAL
ADDRESS
COUNTER
COUNTER
TIMING
GENERATOR
TIMING
GENERATOR
SENSE
AMPLIFIERS
COLUMN
DECODERS
I/O
SELECTOR
WRITE
CLOCK
CLOCK
GENERATOR
INPUT
BUFFERS
ADDRESS BUFFERS
ROW
COLUMN
22
OUTPUT
BUFFERS
OE
CAS
REFRESH
CONTROL
CLOCK
WE
4
RAS
38
– MAIN Board –
IC51
SAA6588T/V2-118
SCOUT
MRO
MPTH
TCON
OSCO
OSCI
VSSD
VDDD
DAVN
SDA
VREF
MPX
VSSA
VDDA
AFIN
MAD
PSWN
SCL
2
1
6
15
11
13
16
14
12
INTERFACE
REGISTER
SIGNAL QUALITY
DECODER
CLOCKED
COMPARATOR
POWER SUPPLY
& RESET
TEST
CONTROL
OSCILLATOR
& CLOCK
PAUSE
DETECTOR
MULTI
PATH
DETECTOR
57kHz
8th ORDER
BAND-PASS FILTER
RDS/RDBS
DECODER
RDS/RDBS
DEMODULATOR
IIC BUS SLAVE
TRANSCEIVER
17
18
CIN
19
LVIN
20
8
7
DATA
CLOCK
DATA
CLOCK
4
4
5
9
10
3
4
5
IC671
BA4908-V3
+
–
+
–
+
–
+
–
OVER VOLTAGE
PROTECT
REGULATOR
1
2 3 4
5
6
7
8
9
10
12
11
NC
TUNER8.7 ANT SW
TUNER5.6 SW
STB
VDD5.6V
AMP
VCC
ANT
COM8.7V
TUNER5.6V
TUNER8.7V
GND
39
IC151
TDA7402TR
34
35
36
37
38
39
40
41
42
43
44
33 32 31
30
29
28
27
26
25
24 23
22
21
20
19
18
16
15
14
13
12
1 2
3 4 5 6
7 8 9 10
11
INPUT
MULTIPLEXER
MAIN SOURCE
SELECTOR
MIXING
SELECTOR
SECOND SOURCE
SELECTOR
MAIN
PHONO
MAIN
CH0
AUX
AM
FM
IN-GAIN
+AUTO ZERO
+
LOUDNESS
SOFTMUTE
VOLUME
TREBLE
BASS
HP
LP
COMPANDER
VOICE
BANDPASS
MUTE
IN-GAIN
LOUDNESS
DIGITAL CONTROL
IIC-BUS
HIGH-CUT
S&H
25kHz
LP
DEMODULATOR
+STEREO ADJUST
+STEREO BLAND
MULTIPATH
DETECTOR
D/A
CONVERTER
PILOT
CANCELATION
PIL DET
PLL
AM/FM
NOISE BLANKER
BEEP
80kHz
LP
17
PULSE
FORMER
QUAL
SUPPLY
SECOND
MAIN
ACIN
MONO-
FADER
MONO-
FADER
MONO-
FADER
MONO-
FADER
MONO-
FADER
MONO-
FADER
SUBWOOFER
+PHASE
CONTROL
MIXER
OUTPUT
SELECTOR
FRONT
REAR
SW
VDD
SCL
SDA
GND
SM
QUAL
MPOUT
MPIN
LEVEL
MPX
AMIF
SEL
SER
FD1L+
FD1L
–
FD1R+
FD1R
–
FD2L+
FD2L
–
FD2R+
FD2R
–
AM
ACINLF
SWINR
SWINL
ACOUTR
ACOUTL
CREF
MUX
MD1
MD1G
MD2
MD2G
ACINLR
ACINRF
ACINRR
OUTLF
OUTLR
OUTRF
OUTRR
OUTSWL
OUTSWR
OUTSSL
OUTSSR
IC701
BA8270F-E2
1
2
3
4
5
5
6
7
8
9
10
14
13
12
11
BUS ON
SWITCH
RESET
SWITCH
BATTERY
SWITCH
BUS ON
RST
BATT
CLK
VREF
DATA
GND
VCC
RST
BUS ON
BUS ON
CLK IN
BU IN
DATA IN
DATA OUT
40
4-19.
IC PIN FUNCTION DESCRIPTION
•
SERVO BOARD IC301 CXD2652AR
Pin No.
Pin Name
I/O
Description
1
MNT0
O
Focus OK signal output to the MD mechanism controller (IC501)
“H” is output when focus is on (“L”: NG)
“H” is output when focus is on (“L”: NG)
2
MNT1
O
Track jump detection signal output to the MD mechanism controller (IC501)
3
MNT2
O
Busy monitor signal output to the MD mechanism controller (IC501)
4
MNT3
O
Spindle servo lock status monitor signal output to the MD mechanism controller (IC501)
5
SWDT
I
Writing serial data signal input from the MD mechanism controller (IC501)
6
SCLK
I
Serial data transfer clock signal input from the MD mechanism controller (IC501)
7
XLAT
I
Serial data latch pulse signal input from the MD mechanism controller (IC501)
8
SRDT
O (3)
Reading serial data signal output to the MD mechanism controller (IC501)
9
SENS
O (3)
Internal status (SENSE) output to the MD mechanism controller (IC501)
10
XRST
I
Reset signal input from the MD mechanism controller (IC501) “L”: reset
11
SQSY
O
Subcode Q sync (SCOR) output to the MD mechanism controller (IC501)
“L” is output every 13.3 msec Almost all, “H” is output
“L” is output every 13.3 msec Almost all, “H” is output
12
DQSY
O
Digital In U-bit CD format subcode Q sync (SCOR) output terminal
“L” is output every 13.3 msec Almost all, “H” is output Not used (open)
“L” is output every 13.3 msec Almost all, “H” is output Not used (open)
13
RECP
I
Laser power selection signal input terminal
“L”: playback mode, “H”: recording mode (fixed at “L” in this set)
“L”: playback mode, “H”: recording mode (fixed at “L” in this set)
14
XINT
O
Interrupt status output to the MD mechanism controller (IC501)
15
TX
I
Recording data output enable signal input terminal
Writing data transmission timing input (Also serves as the magnetic head on/off output)
Not used (fixed at “L”)
Writing data transmission timing input (Also serves as the magnetic head on/off output)
Not used (fixed at “L”)
16
OSCI
I
System clock signal (512Fs=22.5792 MHz) input from the oscillator circuit
17
OSCO
O
System clock signal (512Fs=22.5792 MHz) output terminal Not used (open)
18
XTSL
I
Input terminal for the system clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
19
RVDD
—
Power supply terminal (+3.3V) (digital system)
20
RVSS
—
Ground terminal (digital system)
21
DIN
I
Digital audio signal input terminal when recording mode Not used (fixed at “L”)
22
DOUT
O
Digital audio signal output terminal when playback mode Not used (open)
23
ADDT
I
Recording data input terminal Not used (fixed at “L”)
24
DADT
O
Playback data output to the PCM1718E (IC101)
25
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the PCM1718E (IC101)
26
XBCK
O
Bit clock signal (2.8224 MHz) output to the PCM1718E (IC101)
27
FS256
O
Clock signal (11.2896 MHz) output to the PCM1718E (IC101)
28
DVDD
—
Power supply terminal (+3.3V) (digital system)
29 to 32
A03 to A00
O
Address signal output to the D-RAM (IC307)
33
A10
O
Address signal output to the external D-RAM Not used (open)
34 to 38
A04 to A08
O
Address signal output to the D-RAM (IC307)
39
A11
O
Address signal output to the external D-RAM Not used (open)
40
DVSS
—
Ground terminal (digital system)
41
XOE
O
Output enable signal output to the D-RAM (IC307) “L” active
42
XCAS
O
Column address strobe signal output to the D-RAM (IC307) “L” active
43
A09
O
Address signal output to the D-RAM (IC307)
44
XRAS
O
Row address strobe signal output to the D-RAM (IC307) “L” active
45
XWE
O
Write enable signal output to the D-RAM (IC307) “L” active
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER, 2M BIT D-RAM)
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER, 2M BIT D-RAM)
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