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– 65 –

•

Pin No.

Pin Name

I/O

Function

1

I

I

I-V converted RF signal I input from the optical pick-up block detector

2

J

I

I-V converted RF signal J input from the optical pick-up block detector

3

VC

O

Middle point voltage (+1.65V) generation output terminal

4 to 9

A to F

I

Signal input from the optical pick-up detector

10

PD

I

Light amount monitor input from the optical pick-up block laser diode

11

APC

O

Laser amplifier output terminal to the automatic power control circuit

12

APCREF

I

Reference voltage input terminal for setting laser power

13

GND

—

Ground terminal

14

TEMPI

I

Connected to the temperature sensor    Not used (open)

15

TEMPR

O

Output terminal for a temperature sensor reference voltage    Not used (open)

16

SWDT

I

Writing serial data input from the MD mechanism controller (IC501)

17

SCLK

I

Serial data transfer clock signal input from the MD mechanism controller (IC501)

18

XLAT

I

Serial data latch pulse signal input from the MD mechanism controller (IC501)

19

XSTBY

I

Standby signal input terminal    “L”: standby (fixed at “H” in this set)

20

F0CNT

I

Center frequency control voltage input terminal of internal circuit (BPF22, BPF3T, EQ) input 
terminal

21

VREF

O

Reference voltage output terminal    Not used (open)

22

EQADJ

I

Center frequency setting terminal for the internal circuit (EQ)

23

3TADJ

I

Center frequency setting terminal for the internal circuit (BPF3T)

24

VCC

—

Power supply terminal (+3.3V)

25

WBLADJ

I

Center frequency setting terminal for the internal circuit (BPF22)

26

TE

O

Tracking error signal output to the CXD2652AR (IC301)

27

CSLED

I

Connected to the external capacitor for low-pass filter of the sled error signal

28

SE

O

Sled error signal output to the CXD2652AR (IC301)

29

ADFM

O

FM signal output of the ADIP

30

ADIN

I

Receives a ADIP FM signal in AC coupling

31

ADAGC

I

Connected to the external capacitor for ADIP AGC

32

ADFG

O

ADIP duplex signal (22.05 kHz 

±

 1 kHz) output to the CXD2652AR (IC301)

33

AUX

O

Auxiliary signal (I

3

 signal/temperature signal) output terminal    Not used (open)

34

FE

O

Focus error signal output to the CXD2652AR (IC301)

35

ABCD

O

Light amount signal (ABCD) output to the CXD2652AR (IC301)

36

BOTM

O

Light amount signal (RF/ABCD) bottom hold output to the CXD2652AR (IC301)

37

PEAK

O

Light amount signal (RF/ABCD) peak hold output to the CXD2652AR (IC301)

38

RF

O

Playback EFM RF signal output to the CXD2652AR (IC301)

39

RFAGC

I

Connected to the external capacitor for RF auto gain control circuit

40

AGCI

I

Receives a RF signal in AC coupling

41

COMPO

O

User comparator output terminal    Not used (open)

42

COMPP

I

User comparator input terminal    Not used (fixed at “L”)

43

ADDC

I

Connected to the external capacitor for cutting the low band of the ADIP amplifier

44

OPO

O

User operational amplifier output terminal    Not used (open)

45

OPN

I

User operational amplifier inversion input terminal    Not used (fixed at “L”)

46

RFO

O

RF signal output terminal

47

MORFI

I

Receives a MO RF signal in AC coupling

48

MORFO

O

MO RF signal output terminal

– 66 –

•

Pin No.

Pin Name

I/O

Function

1 to 5

TIN3 to TIN7

I/O

Input of the 4

×

8 matrix test keys (“L” is always output, except in test mode)     Not used (open)

6

LOAD

O

Loading motor control signal output to the motor driver (IC305)    “H” active    *1

7

EJECT

O

Loading motor control signal output to the motor driver (IC305)    “H” active    *1

8, 9

NCO

O

Not used (open)

10

MDMON

O

Power supply on/off control signal output of the MD mechanism deck section main power supply 
and loading motor drive (IC305) power supply    “H”: power on

11

E-SW

I

Inputs the disc loading completion detect switch detection signal
“L”: When completed of the disc loading operation

12

AG-OK

O

Output of aging status in test mode   “L”: under aging,  “H”: aging completed    Not used (open)

13

ADJ-OK

O

Output of status when aging completed in test mode    “L”: aging NG, “H”: aging OK
Not used (open)

14 to 17

NCO

O

Not used (open)

18

DFCTSEL

I

Select whether defect function is used for the CXD2652AR (IC301)
“L”: used this function , “H”: not used this function (fixed at “H” in this set)

19

DPLLSEL

I

Select whether digital PLL function is used for the CXD2652AR (IC301)
“L”: used this function , “H”: not used this function (fixed at “H” in this set)

20

EMPHSEL

I

Select whether emphasis signal output from pin or unilink data
“L”: outputs from both pin and unilink data, “H”: output from pin only (fixed at “H” in this set)

21

LOCK

O

Mini-disc lock detection signal output to the master controller (IC700)    “H”: lock

22

NCO

O

Not used (open)

23

2M/4M

I

Select whether D-RAM capacitance 2M bit or 4M bit    “L”: 4M bit (external D-RAM) , “H”: 2M 
bit (internal D-RAM of CXD2652AR) (fixed at “L” in this set)

24, 25

NCO

O

Not used (open)

26

MNT0

I

Focus OK signal input from the CXD2652AR (IC301)
“H” is input when focus is on (“L”: NG)

27

MNT1

I

Track jump detection signal input from the CXD2652AR (IC301)

28

MNT2

I

Busy monitor signal input from the CXD2652AR (IC301)

29

MNT3

I

Spindle servo lock status monitor signal input from the CXD2652AR (IC301)

30

RESET

I

System reset signal input from the master controller (IC700), reset signal generator (IC801) and 
reset switch (S900)    “L”: reset    For several hundreds msec. after the power supply rises, “L” is 
input, then it changes to “H”

31

EXTAL

O

Main system clock output terminal (10 MHz)

32

XTAL

I

Main system clock input terminal (10 MHz)

33

VSS

—

Ground terminal

34

TX

O

Sub system clock output terminal (32.768 kHz)    Not used (open)

35

TEX

I

Sub system clock input terminal (32.768 kHz)    Not used (fixed at “L”)

36

AVSS

—

Ground terminal (for A/D converter)

37

AVREF

I

Reference voltage input terminal (+5V) (for A/D converter)

38

INIT

I

Initial reset signal input terminal (A/D input) (fixed at “H”)

39

TEMP

I

Temperature sensor (TH501) input terminal (A/D input)

40

ACNT

I

Select the number of load/eject aging times (A/D input)
0H – 54H (30 times), 55H – OA9H (20 times), OAAH – OFFH (10 times)

41

DO-SEL

I

Select the digital output bits (A/D input)

42

EE-CS

O

Chip select signal output to the external EEPROM device    Not used (open)

43

EE-CKO

O

Serial data transfer clock signal output to the external EEPROM device    Not used (open)

44

EE-SIO

I/O

Two way data bus with the external EEPROM device    Not used (open)

45

MD-SO

O

Writing serial data signal output to the CXD2652AR (IC301) and CXA2523R (IC302)

46

LINKOFF

O

Unilink on/off control signal output for the SONY bus    “L”: link on, “H”: link off

– 67 –

Pin No.

Pin Name

I/O

Function

47

UNIREQ

O

Data request signal output terminal (for SONY bus)    “H”: request on    Not used (open)

48

UNICKIO

I/O

Serial clock signal input from the master controller (IC700) or serial clock signal output to the 
SONY bus interface (IC600) and master controller (IC700) (for SONY bus)

49

UNISI

I

Serial data input from the SONY bus interface (IC600)

50

UNISO

O

Serial data output to the SONY bus interface (IC600)

51

MD-CKO

O

Serial data transfer clock signal output to the CXD2652AR (IC301) and CXA2523R (IC302)

52

MD-SI

I

Reading serial data signal input from the CXD2652AR (IC301)

53

NCO

O

Not used (open)

54

SENS

I

Internal status (SENSE) input from the CXD2652AR (IC301)

55

CC-XINT

I

Interrupt status input from the CXD2652AR (IC301)

56

LIMIT-IN

I

Detection input from the sled limit-in detect switch
The optical pick-up is inner position when “L”

57

EJT-KEY

I

Eject request signal input terminal    “L”: eject on    Not used (fixed at “H”)

58

ERROR-PWM

O

PWM error monitor output terminal (C1and ATER is output when test mode)    Not used (open)

59

MD-RST

O

Reset signal output to the PCM1718E (IC101), CXD2652AR (IC301) and BH6511FS (IC303)    
“L”: reset

60

BU-IN

I

Battery detect signal input from the SONY bus interface (IC600) and battery check circuit
“H”: battery on

61

BUS-ON

I

SONY bus on/off control signal input from the master controller (IC700)    “L”: bus on

62

SQSY

I

Subcode Q sync (SCOR) input from the CXD2652AR (IC301)
“L” is input every 13.3 msec    Almost all, “H” is input

63

C-SW

I

Inputs the disc loading start or disc eject completion detect switch detection signal
“L”: When start or eject completed of the disc loading operation

64

MD-LAT

O

Serial data latch pulse signal output to the CXD2652AR (IC301) and CXA2523R (IC302)

65

MD-ON

O

Power supply on/off control signal output of the MD mechanism deck section main power supply  
“H”: power on

66

DEEMP

O

Emphasis on/off control signal output to the PCM1718E (IC101)    “H”: emphasis on

67

A-MUTE

O

Audio muting on/off control signal output terminal

68

NCO

O

Not used (open)

69

TSTCKO

O

Output of clock signal for the test mode display    Not used (open)

70

TSTSO

O

Output of data for the test mode display    Not used (open)

71

TSTMOD

I

Setting terminal for the test mode    “L”: test mode, “H”: normal mode

72

VCC

—

Power supply terminal (+5V)

73

NIL

I

Not used (fixed at “H”)

74 to 77

TOUT0 to TOUT3

O

Output of the 4

×

8 matrix test keys     Not used (open)

78 to 80

TIN0 to TIN2

I/O

Input of the 4

×

8 matrix test keys (“L” is always output, except in test mode)     Not used (open)

*1  Loading motor (M903) control

LOAD (pin 6)

“H”

“L”

“H”

“L”

EJECT (pin 7)

“L”

“H”

“H”

“L”

Terminal

Operation

IN

OUT

BRAKE

STOP

– 68 –

•

Pin No.

Pin Name

I/O

Function

1 to 7

NC

O

Not used (open)

8

VCC

—

Power supply terminal (+5V)

9

PLL SI

I

PLL serial data input terminal    Not used (open)

10

PLL SO

O

PLL serial data output terminal    Not used (open)

11

PLL CKO

O

PLL serial data transfer clock signal output terminal    Not used (open)

12

NOSE-SW

I

Front panel block remove/attach detection signal input terminal
“L”: front panel is attached

13

LCD SO

O

Serial data output to the liquid crystal display driver (IC801)

14

LCD CKO

O

Serial data transfer clock signal output to the liquid crystal display driver (IC801)

15

BEEP

O

Beep sound drive signal output terminal

16

DBMOD2

O

D-BASS mode control signal output terminal    Not used (open)

17

DOOR-SW

I

Front panel open/close detection signal input    “L” is input when the front panel is closed
Not used (open)

18, 19

NC

O

Not used (open)

20

UNI SI

I

Serial data input from the SONY bus interface (IC600)

21

UNI SO

O

Serial data output to the SONY bus interface (IC600)

22

UNI CKIO

I/O

Serial clock signal output to the MD mechanism controller (IC501) and SONY bus interface 
(IC600) or serial clock signal input from the MD mechanism controller (IC501) (for SONY bus)

23

NC

O

Not used (open)

24

SIRCS

I

Sircs remote control signal input terminal    Not used (fixed at “L”)

25

PACK-IND

O

LED drive signal output of the MD disc slot illumination and 

6 indicator    “H”: LED on

“H” is output to turn on LED when front panel is opened    Not used (open)

26

VOL SO

O

Serial data output for the electrical volume    Not used (open)

27

VOL CKO

O

Serial data transfer clock signal output for the electrical volume    Not used (open)

28

DSTSEL0

I

Destination setting terminal
(Except German models: fixed at “H”, German model: fixed at “L”)

29

SYSRST

O

System reset signal output to the MD mechanism controller (IC501) and SONY bus interface 
(IC600)    “L”: reset

30

DSTSEL1

I

Destination setting terminal
(US, Canadian models: fixed at “H”, E model: fixed at “L”)

31

DBMOD1

O

D-BASS mode control signal output terminal    Not used (open)

32

TESTIN

I

Setting terminal for the test mode    “L”: test mode, Normally: fixed at “H”

33

VSS

—

Ground terminal

34

C

—

Connected to coupling capacitor for the power supply

35

NS-MASK

O

Discharge control signal output for the noise detection circuit   “H”: discharge
Used for the MDX-C5960R/C5970R only (MDX-C5970: Not used (open))

36

BUS- ON

O

Bus on/off control signal output to the MD mechanism controller (IC501) and SONY bus 
interface (IC600)    “L”: bus on

37

AD-ON

O

A/D converter power control signal output terminal
When the KEYACK (pin &ª) that controls reference voltage power for key A/D conversion input 
is active, “L” is output from this terminal to enable the input

38

DVCC

—

Power supply terminal (+5V) (for D/A converter)

39

DVSS

—

Ground terminal (for D/A converter)

40

LCDANG

O

View field angle control signal is output when front panel is fully opened
“H”: front panel is fully opened

41

VOL CE

O

Chip enable signal output for the electrical volume    Not used (open)

42

AVCC

—

Power supply terminal (+5V) (for A/D converter)