Sony MDX-62 Service Manual ▷ View online
– 36 –
– Main Section –
1
IC600
!º
(X2)
2.7 Vp-p
71 ns
2
IC600
!¢
(XT1)
2.6 Vp-p
30.4
µ
s
3
IC500
4
(LRCK)
2.8 Vp-p
22.7
µ
s
4
IC500
6
(BCK)
2.8 Vp-p
354 ns
5
IC500
1
(XT1)
3.2 Vp-p
89 ns
– 37 –
• IC Block Diagrams
– Servo Section –
IC100 CXA2523AR
–1
–2
+
–
IVR
BB
+
–
IVR
AA
+
–
IVR
CC
+
–
IVR
DD
+
–
IVR
+
–
EE
EE'
EFB
TESW
PTGR
48
MORFO
47
MORFI
46
RFO
45
OPN
44
OPO
43
ADDC
42
COMPP
41
COMPO
40
AGCI
39
RF AGC
38
RF
37
PEAK
36 BOTM
35 ABCD
34 FE
33 AUX
32 ADFG
31 ADAGC
30 ADIN
29 ADFM
28 SE
27 CSLED
26 TE
25 WBLADJ
24
VCC
23
3TADJ
22
EQADJ
21
VREF
20
F0CNT
19
XSTBY
18
XLAT
17
SCLK
16
SWDT
15
TEMPR
14
TEMPI
13
GND
12
APCREF
11
APC
10
PD
9
F
8
E
7
D
6
C
5
B
4
A
3
VC
VI CONV
BGR
VREF
SCRI - PARA
DECODE
+ –
–
+
AUXSW
COMMAND
+
–
IVR
GSW
+
–
FF
FBAL
FF'
TG
SEA
–
+
–
+
–1
–2
TG
TEA
WBL
3T
EQ
–
–
+
+
+
+
–
–
–
–
–
–
DET
ADIP
AGC
WBL
BPF22
BPFC
ABCDA
FEA
WBL
ATA
–
+
CVB
+
–
RFA1
–
–
–
–
1
2
–
–
–
–
–
1
2
2
GRVA
OFST
RFA2
GRV
HLPT
PTGR
–2
–1
–1
–2
BOTTOM
PEAK
RF AGC
EQ
EQ
DET
P-P
WBL
3T
WBL
TEMP
PBH
–
+
USROP
+
–
USRC
3T
BPF3T
PEAK3T
1
I
2
J
RFA3
PBSW
AUX
SW
IV
ESW
EBAL
– 38 –
IC200 CXD2652AR
100 99 98 97 96 95
94 93
EFMO
DVSS
TEST3
TEST2
TEST1
FGIN
SPFD
SPRD
92
SFDR
91
SRDR
90
FS4
89
FRDR
88
FFDR
87
DVDD
86
TFDR
85
TRDR
84
LDDR
83
APCREF
82
DTRF
81
CKRF
80
XLRF
79
F0CNT
78
ADFG
77
APC
76
DCHG
75 AUX2
74 TE
73 SE
72 AVSS
71 ADRB
70 ADRT
69 AVDD
68 ADIO
61 CLTV
60 FILO
59 FILI
58 PCO
57 PDO
55 RFI
56 AVSS
54 BIAS
53 AVDD
52 ASYI
51 ASYO
67 VC
66 AUX1
65 FE
64 ABCD
63 BOTM
62 PEAK
50
MVCI
49
D3
48
D2
47
D0
46
D1
45
XWE
44
XRAS
43
A09
42
XCAS
41
XOE
40
DVSS
39
A11
38
A08
37
A07
36
A06
35
A05
34
A04
33
A10
32
A00
31
A01
30
A02
29
A03
28
DVDD
26
XBCK
27
FS256
25
LRCK
24
DADT
23
ADDT
22
DOUT
21
DIN
20
DVSS
19
NC
18
XTSL
17
OSCO
16
OSCI
15
TX
14
XINT
13
RECP
12
DQSY
11
SQSY
10
XRST
9
SENS
8
SRDT
7
XLAT
6
SCLK
5
SWDT
4
MNT3
3
MNT2
2
MNT1
1
MNT0
PWM
GENERATOR
AUTO
SEQUENCER
SERVO
DSP
CPU I/F
MONITOR
CONTROL
CONTROL
SPINDLE
SERVO
EACH
BLOCK
BLOCK
EACH
BLOCK
BLOCK
DIGITAL
AUDIO
I/F
SAMPLING
RATE
CONVERTER
CLOCK
GENERATOR
SUBCODE
PROCESSOR
EACH
BLOCK
BLOCK
A/D
CONVERTER
ANALOG
MUX
EFM/ACIRC
ENCODER/
DECODER
PLL
SHOCK RESISTANT
MEMORY CONTROLLER
ATRAC
ENCODER/DECODER
ADIP
DECODER
COMP
ADDRESS/DATA BUS A00 - A11, D0 - D3
IC300 MPC17A38ZVMEL
15
13
12
11
DC/DC
CONVERTER
CLK
DETECTOR
PRE-DRIVER
CONTROL
DRIVER
PRE-DRIVER
CONTROL
DRIVER
PRE-DRIVER
CONTROL
DRIVER
PRE-DRIVER
CONTROL
DRIVER
36
35 34 33
32 31 30 29
28 27
26 25 24
23
22 21
20 19
18
17
16
1
2 3 4
5 6 7 8 9 10
14
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
PI4
PGND
PGND
RO3
VD
RO4
PGND
FO4
VD
F/R4
FO3
VD
FI3
RI3
VG
GND
PS
OE
RI2
FI2
VD
FO2
VD
RO2
PGND
RO1
PGND
PGND
FO1
VD
FI1
RI1
GND
CLK
VC
LG
CLOCK
– 39 –
IC540 SM5852FS-E2
IC500 PCM1717E-ST2
IC700, 701 LB1638MTP-T1
– Main Section –
1
2
3
4
5
6
7
8
9
10
16
15
14
13
12
11
INPUT
INTERFACE
DIGITAL
FILTER
MODE
CONTROL
LOWPASS
FILTER
CMOS
AMP
5 LEVEL
DAC
NOISE SHAPER
LOWPASS
FILTER
CMOS
AMP
5 LEVEL
DAC
CLK
CONTROL
20
19
18
17
XTO
CLKO
MUTE
DM1
DM0
DM1
DM0
RSTB
FORMAT
D/C L
VOUTL
VCC
AGND
VOUTR
D/C R
ZERO
BCKIN
DIN
LRCIN
VDD
DGND
XTI
IC520 TC7W74FU (TE12R)
6
CLR
7
PR
8
VCC
5
Q
R
S
Q
3
Q
2
D
4
GND
1
CK
Q
D
C
1
2
2
3
4
5
6
7
8
9
10
16
15
14
13
12
11
DIGITAL
SIGNAL
PROCESSOR
OUTPUT
INTERFACE
SYSTEM
CLOCK
INPUT
INTERFACE
SEQUENTIAL
CONTROL
MUTE
CONTROL
MODE
CONTROL
LRCI
BCKI
BCKI
DI
CLK
VSS
RSTN
TESTN
MUTEN
DB/DS
MOD2
MOD2
MOD1
OPT
VDD
LRCO
BCKO
DOUT
1
2
3
4
5
6
7
8
9
10
GND
IN1
VCC
IN2
GND
N.C.
OUT2
VS
OUT1
N.C.
CONTROL LOGIC
IC900 BA8272F-E2
– Power Section –
1
2
3
4
5
6
7
8
9
10
14
13
12
11
VCC
BUS ON
LINK OFF
CLK OUT
DATA OUT
DATA IN
BUS RESET
BUS DATA
VREF
BUS CLK
GND
BUS ON IN
BUS ON OUT
RESET
RESET
SWITCH
IC970 TL5001CPS-E20
REFERENCE
VOLTAGE
S.C.P.
COMPARATOR 1
SWITCH
'ON'
AT
'H'
'H'
PWM
COMPARATOR
S.C.P.
COMPARATOR 2
DEAD-TIME
COMPARATOR
S.C.P.
LATCH
OSC
U.V.L.O
ERROR
AMP
–
+
+
+
–
–
+
–
+
–
–
–
+
+
5
6
7
8
1
2
3
4
OUT
VCC
FEED BACK
INPUT
SCP
DEAD-TIME
CONTROL
RT
GND
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