Sony DSX-S100 Service Manual ▷ View online
DSX-S100
29
21
22
29
30
23
24
40
FIL
GND
SDA
SCL
OUT
-FR
OUT
-FL
OUT
-RR
OUT
-RL
SUB-R
SUB-L
SAOUT
SADA
MIN1
MIN2
EBIAS2
DS2-R
DS1-R
DS3-R
SACLK
39
38
37
VCC
36
27
28
25
26
31
32
33
34
35
20
19
12
11
18
17
1
BUS-R
BUS-L
TU-R
TU-L
CD-L
AUX-R
AUX-G
AUX-L
PD-R
PD-G
PD-L
FP1
FN2
FP2
EBIAS1
DS2-L
DS1-R
DS3-R
FN1
2
3
4
CD-R
5
14
13
16
15
10
9
8
7
6
I2C BUS
LOGIC,
VCO
FADER
FADER
FADER
HPF
LPF
GND
ISO AMP
GND
ISO AMP
180
q/0q
3 BAND P-EQ (TONE CONTROL)
7 BAND
SPECTRUM ANALYZER
/LEVEL METER
EFFECT
VOLUME/MUTE
INPUT GAIN
INPUT SELECTOR (3 SIGLE-END AND 3 STEREO IS O)
FADER
FADER
SPEANA
LVL METER
LVL METER
SPEANA
GND
ISO AMP
GND
ISO AMP
GND
ISO AMP
GND
ISO AMP
IC401 BD3447AFV-E2
DSX-S100
30
IC601 BA8271F-E2
1
2
3
4
5
6
7
8
9
10
14
13
12
11
VCC
BUS ON
LINK OFF
CLK OUT
DA
TA
OUT
D
ATA
IN
BUS RESET
BUS DA
TA
VREF
BUS CLK
GND
BUS ON IN
BUS ON OUT
RESET
RESET
SWITCH
IC801 BD9070FP-E2
PVIN
24
16
N.C.
23
INV
18
VDD
15
N.C.
14
OVP
VDD
17
FLG 10
N.C. 11
HSDSW 12
HSDSW 13
HSDSW 13
N.C.
20
FB
19
SW
22
SW
21
VIN 2
VREGB 1
HSDCTL 9
EN 8
RT 7
GND 6
PGND 5
N.C. 4
N.C. 3
CONTROL
LOGIC
DRV
LOGIC
UVLO,
TSD,
HSD UVLO
HSD UVLO
UVLO, TSD,
OVP, OCP, SCP
CHARGE
PUMP
SOFT
START
OCD
SLOPE
OSC
VREF
SYNC
VREG
UVLO
TSD
+
–
–
+
+
–
+
HSD
UVLO
SCP
–
+
SCP
OVP
OCP
+
–
OVP
R
S
PWM
ERR
PVIN
25
–
+
OCP
UVLO
TSD
DRV
DSX-S100
31
• IC Pin Function Description
MAIN BOARD IC201 TC94A92FG-301 (M) (DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VCOI
I
DSP VCO control voltage input terminal
2
RVDD3
-
Power supply terminal (+3.3V)
3
SLCO
O
EFM slice level output terminal Not used
4
RFI
I
RF signal input terminal Not used
5
RFRPI
I
RF ripple signal input terminal Not used
6
RFEQO
O
EFM slice level output terminal Not used
7
DCOFC
O
Not used
8
AGCI
I
RF signal amplitude adjustment amplifi cation input terminal Not used
9
RFO
O
RF signal generation amplifi cation output terminal Not used
10
RVSS3
-
Ground terminal
11
FNI2
I
Main beam input terminal (Connect with pin diode C) Not used
12
FNI1
I
Main beam input terminal (Connect with pin diode A) Not used
13
FPI2
I
Main beam input terminal (Connect with pin diode D) Not used
14
FPI1
I
Main beam input terminal (Connect with pin diode B) Not used
15
TPI
I
Sub beam amplifi cation input terminal (Connect with pin diode F) Not used
16
TNI
I
Sub beam amplifi cation input terminal (Connect with pin diode E) Not used
17
VRO
O
Reference voltage (+1.65V) output terminal Not used
18
AVSS3
-
Ground terminal
19
MDI
I
Monitor photo diode amplifi cation input terminal Not used
20
LDO
O
Laser diode amplifi cation output terminal Not used
21
FE/SBAD
O
Subbeam addition signal output/RF peak detecting phase signal output for hologram selection
terminal Not used
terminal Not used
22
RFZI
I
RF ripple zero crossing signal input terminal Not used
23
RFRP
O
RF ripple signal output terminal Not used
24
TEI
I
Tracking error signal input terminal Not used
25
AVDD3
-
Power supply terminal (+3.3V)
26
FOO
O
Focus servo equalizer signal output terminal Not used
27
TRO
O
Tracking servo equalizer signal output terminal Not used
28
VSS
-
Ground terminal
29
FMO
O
Feeding servo equalizer signal output terminal Not used
31
DMO
O
Disc servo equalizer signal output terminal Not used
32
VDDI-3
-
Power supply terminal (+1.5V)
33
Plo8/TxD (SPDIF)
-
Not used
34
Plo9/RxD (DATA)
-
Not used
35
Plo10/RTS (BLK)
-
Not used
36
Plo11/CTS (LRCK)
-
Not used
37
CDMON0 (DFCT)
-
Not used
38
CDMON1 (FOK)
-
Not used
39
CDMON2 (RFOK)
-
Not used
40
CDMON3 (SBSY)
O
Not used
41
DVSS3R
-
Ground terminal
42
RO
O
R channel data (positive) output terminal
43
DVDD3R
-
Power supply terminal (+3.3V)
44
DVDD3L
-
Power supply terminal (+3.3V)
45
LO
O
L channel data (positive) output terminal
46
DVSS3L
-
Ground terminal
47
XVSS3
-
Ground terminal
48
XI
I
System clock input terminal (16.9344 MHz)
49
XO
O
System clock output terminal (16.9344 MHz)
50
XVDD3
-
Power supply terminal (+3.3V)
51
VDD1-2
-
Power supply terminal (+1.5V)
52
VSS
-
Ground terminal
53
DEC_REQ
O
Request signal output to the USB controller
54
BSIF-REQ
O
Request signal output to the USB controller
55
BSIF-GATE
I
Gate signal input from the USB controller
56
DEC_XMUTE
O
Muting on/off control signal output to the USB controller
57
DATA
I
Audio data input from the USB controller
DSX-S100
32
Pin No.
Pin Name
I/O
Description
58
BCK
I
Bit clock signal input from the USB controller
59
LRCK
I
L/R sampling clock signal (44.1 kHz) input terminal for audio data input
60
ZDET
O
Zero detection signal output terminal
61
VDD3
-
Power supply terminal (+3.3V)
62, 63
BUS0, BUS1
I/O
Bus data input/output with the USB controller
64
BUS2 (SO)
O
Serial data output to the USB controller
65
BUS3 (SI)
I
Serial data input from the USB controller
66
BUCK (CLK)
I
Bus clock signal input from the USB controller
67
/CCE
I
Chip enable signal input from the USB controller
68
MS
I
I/F mode selection signal input terminal Fixed at “H” in this set
69
/RST
I
Reset signal input from the USB controller
70
TEST
I
Setting terminal for test mode Normally fi xed at “L”
71
VDD1-2
-
Power supply terminal (+1.5V)
72
VSS
-
Ground terminal
73
/SRAMSTB
I
Strobe signal input from the USB controller “L”: standby mode
74
VDDM1
-
Power supply terminal (+1.5V)
75
PDO
O
Phase error margin signal between EFM signal and PLCK signal output terminal Not used
76
TMAX
O
TMAX detection result output terminal Not used
77
LPFN
I
Inverted signal input from the operation amplifi er for PLL loop fi lter Not used
78
LPFO
O
Signal output from the operation amplifi er for PLL loop fi lter Not used
79
PVREF
I
Reference voltage (+1.65V) input terminal Not used
80
VCOF
O
Terminal for VCO fi lter Not used
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