Sony CDX-V7800X Service Manual ▷ View online
17
• IC514 CL8830-PE0 (MPEG DECODER)
Pin No.
Pin Name
I/O
Pin Description
1
RESERVED
I
Fixed at L in this set.
2 – 4
HDATA0 – 2
I/O
8-bit bi-directional host data bus 0 – 2 input/output
5
VDD
—
Power supply pin (+3.3 V)
6
HDATA3
I/O
8-bit bi-directional host data bus 3 input/output
7
VSS
—
Ground
8 – 11
HDATA4 – 7
I/O
8-bit bi-directional host data bus 4 – 7 input/output
12
VDD2.5
—
Power supply pin (+2.5 V)
13
RESET
I
Hardware reset input
14
VSS
—
Ground
15
WAIT
O
Host wait output
16
INT
O
Host interrupt output
17
VDD
—
Power supply pin (+3.3 V)
18
NC
O
Not used. (Open)
19
VSS
—
Ground
20 – 26
NC
O
Not used. (Open)
27
VDD
—
Power supply pin (+3.3 V)
28
NC
O
Not used. (Open)
29
VSS
—
Ground
30 – 35
NC
O
Not used. (Open)
36
VDD
—
Power supply pin (+3.3 V)
37
NC
O
Not used. (Open)
38
VSS
—
Ground
39
NC
O
Not used. (Open)
40
VDD2.5
—
Power supply pin (+2.5 V)
41
NC
O
Not used. (Open)
42
VSS
—
Ground
43 – 46
NC
O
Not used. (Open)
47
VDD
—
Power supply pin (+3.3 V)
48
NC
O
Not used. (Open)
49
VSS
—
Ground
50, 51
NC
O
Not used. (Open)
52
RESERVED
I
Fixed at L in this set.
53, 54
MDATA15, 0
I/O
Memory data 15 and 0 input/output
55
VDD
—
Power supply pin (+3.3 V)
56
MDATA14
I/O
Memory data 14 input/output
57
VSS
—
Ground
58 – 60
MDATA1, 13, 2
I/O
Memory data 1, 13 and 2 input/output
61
VDD
—
Power supply pin (+3.3 V)
62
MDATA12
I/O
Memory data 12 input/output
63
VSS
—
Ground
64
MDATA3
O
I/O
Memory data 3 input/output
65
VDD2.5
—
Power supply pin (+2.5 V)
66
MDATA11
I/O
Memory data 11 input/output
67
VSS
—
Ground
68
MDATA4
I/O
Memory data 4 input/output
69
VDD
—
Power supply pin (+3.3 V)
70
MDATA10
I/O
Memory data 10 input/output
71
VSS
—
Ground
72 – 74
MDATA5, 9, 6
I/O
Memory data 5, 9 and 6 input/output
75
VDD
—
Power supply pin (+3.3 V)
76
MDATA8
I/O
Memory data 8 input/output
77
VSS
—
Ground
18
Pin No.
Pin Name
I/O
Pin Description
78
MDATA7
I/O
Memory data 7 input/output
79
LDQM
O
SDRAM LDQM output
80
UDQM
O
SDRAM UDQM output
81
VDD
—
Power supply pin (+3.3 V)
82
MWE
O
SDRAM write enable output
83
VSS
—
Ground
84
SD-CLK
O
SDRAM system clock output
85
SD-CAS
O
SDRAM column address output
86
SD-RAS
O
SDRAM row address output
87
VDD
—
Power supply pin (+3.3 V)
88
SD-CS1
O
SDRAM bank select 1 output (Not used in this set)
89
VSS
—
Ground
90
SD-CS0
O
SDRAM bank select 0 output
91
VDD2.5
—
Power supply pin (+2.5 V)
92
NC
O
Not used. (Open)
93
VSS
—
Ground
94
NC
O
Not used. (Open)
95
VDD
—
Power supply pin (+3.3 V)
96
MADDR9
O
Memory address 9 output
97
VSS
—
Ground
98 – 100
MADDR11, 8, 10
O
Memory address 11, 8 and 10 output
101
VDD
—
Power supply pin (+3.3 V)
102
MADDR7
O
Memory address 7 output
103
VSS
—
Ground
104 – 106
MADDR0, 6, 1
O
Memory address 0, 6 and 1 output
107
VDD
—
Power supply pin (+3.3 V)
108
MADDR5
O
Memory address 5 output
109
VSS
—
Ground
110 – 112
MADDR2, 4, 3
O
Memory address 2, 4 and 3 output
113
VDD
—
Power supply pin (+3.3 V)
114
MADDR12
O
Memory address 12 output
115
VSS
—
Ground
116
MADDR13
O
Memory address 13 output
117
VDD2.5
—
Power supply pin (+2.5 V)
118
MADDR14
O
Memory address 14 output
119
VSS
—
Ground
120 – 122
MADDR15 – 17
O
Memory address 15 – 17 output
123
VDD
—
Power supply pin (+3.3 V)
124
MADDR18
O
Memory address 18 output
125
VSS
—
Ground
126, 127
MADDR19, 20
O
Memory address 19 and 20 output
128
ROM-CS
O
ROM chip select output
129
RESERVED
I
Fixed at L in this set.
130
NC
O
Not used. (Open)
131, 132
GND
—
Ground
133
RESERVED
I
Fixed at L in this set.
134
VDD
—
Power supply pin (+3.3 V)
135
RESERVED
I
Fixed at L in this set.
136
VSS
—
Ground
137 – 141
RESERVED
I
Fixed at L in this set.
142, 143
VDATA0, 1
O
Video data bus 0 and 1 output
144
VDD2.5
—
Power supply pin (+2.5 V)
145
VDATA2
O
Video data bus 2 output
19
Pin No.
Pin Name
I/O
Pin Description
146
VSS
—
Ground
147
RESERVED
I
Fixed at L in this set.
148
VDATA3
O
Video data bus 3 output
149
VDD
—
Power supply pin (+3.3 V)
150
VDATA4
O
Video data bus 4 output
151
VSS
—
Ground
152
VDATA5
O
Video data bus 5 output
153
RESERVED
I
Fixed at L in this set.
154, 155
VDATA6, 7
O
Video data bus 6 and 7 output
156
RESERVED
I
Fixed at L in this set.
157
HSYNC
I/O
Horizontal sync input/output
158
VSYNC
I/O
Vertical sync input/output
159
NC
O
Not used. (Open)
160
VDD
—
Power supply pin (+3.3 V)
161
NC
O
Not used. (Open)
162
VSS
—
Ground
163, 164
DA-DATA1, 2
O
Serial audio samples relative to DA-BCK clock.
165
VDD2.5
—
Power supply pin (+2.5 V)
166
DA-LRCK
O
PCM left-right clock output
167
DA-BCK
O
PCM bit clock output
168
VDD2.5
—
Power supply pin (+2.5 V)
169
DA-XCK
O
Audio external frequency clock output
170
VSS
—
Ground
171
DAI-DATA
I
PCM input data, two channels.
172
DAI-LRCK
I
PCM input left-right clock
173
DAI-BCK
I
PCM input bit clock
174
RESERVED
I
Fixed at L in this set.
175
VDD
—
Power supply pin (+3.3 V)
176
A-VDD
—
Analog power supply pin (+3.3 V)
177
VCLK
I
Video clock input
178
SYSCLK
I
system clock input
179
A-VSS
—
Analog ground
180
CD-DATA
I
Serial CD data input
181
VDD
—
Power supply pin (+3.3 V)
182
CD-LRCK
I
Programmable polarity 16-bit word synchronization to the decoder (right channel HIGH).
183
VSS
—
Ground
184
CD-BCK
I
CD bit clock input
185
CD-C2PO
I
Asserted HIGH indicated a corrupted byte.
186 – 190
RESERVED
I
Fixed at L in this set.
191
NC
O
Not used. (Open)
192
RESERVED
I
Fixed at L in this set.
193
VDD
—
Power supply pin (+3.3 V)
194
NC
O
Not used. (Open)
195
VSS
—
Ground
196
VSS1
—
Ground
197
VDD2.5
—
Power supply pin (+2.5 V)
198
VSS1
—
Ground
199
VSS
—
Ground
200
VSS1
—
Ground
201
HOST8SEL
I
Host select input
202 – 204
HADDR0 – 2
I
Host address bus 0 – 2 input
205
DTACKSEL
I
Data acknowledge select input
206
CS
I
Host chip select input
20
Pin No.
Pin Name
I/O
Pin Description
207
R/W
I
Read/write strobe input in I mode.
208
RD
I
Read strobe input in M mode.
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