Sony CDX-V5800 Service Manual ▷ View online
29
CDX-V5800
• IC PIN DESCRIPTIONS
• IC500 BU9536KS2 (RF AMP, DIGITAL SERVO) (SERVO BOARD (1/2))
Pin No.
Pin Name
I/O
Pin Description
1
AVDD1
—
Analog power supply pin (+3.3 V)
2
AC
I
A+C voltage signal input from optical pick-up block
3
BD
I
B+D voltage signal input from optical pick-up block
4
VBIAS
O
Bias level (VDD/2) signal output
5
E
I
E voltage signal input from optical pick-up block
6
F
I
F voltage signal input from optical pick-up block
7
AGND1
—
Analog ground pin
8
FEN
I
Focus error amplifier feedback signal input
9
FEO
O
Focus error signal output
10
PKC
O
RF signal peak detection capacitance connected pin
11
BTC
O
RF signal bottom detection capacitance connected pin
12
PD
I
APC photo detecter signal input
13
LD
O
APC laser drive signal output
14
PCO
O
PLL PCO signal output
15
FCO
O
PLL FCO-DAC signal output
16
ASY
I
Asymmetry revice and ccomparator slice capacitor install pin
17
JUMPO
O
Tracking jump pulse signal output
18
TDOUT
O
Tracking drive signal output
19
SDIN
I
Sled signal input
20
SDOUT
O
Sled drive signal output
21
FDOUT
O
Focus drive signal output
22
CLVOUT
O
CLV drive signal output
23
CLK88
O
Clock signal output for driver IC Not used in this set. (Open)
24
LON
O
Laser on control signal output
25
CLK
O
Clock signal output Not used in this set. (Open)
26
MCK
I
Transfer clock signal input for sub Q and command
27
DIN/DOUT
I/O
Command signal input/status, sub-Q signal output
28
R/W
I
Read/write signal input for command
29
RESETX
I
System reset signal input “L”: reset
30
BUSY
O
Busy signal output
31
SUBSYQ
O
Sub cord synchronizing signal output
32
SUBDATA
O
Sub cord data signal output
33
SUBCK
I
Sub cord bit clock signal input Not used in this set. (Fixed at “L”.)
34
WFCK
O
Disc frame synchronizing signal output
35
DOUTA
O
Audio serial data signal output
36
LRCK
O
Audio LR signal output
37
DCK
O
Audio serial bit clock signal output
38
EFLAG
I/O
Error flag signal input/output
39
BUFO
O
X'tal 16.9344 MHz buffer signal output Not used in this set. (Open)
40
XPLCK
I/O
XPLCK signal input/output Not used in this set. (Open)
41
DVDD
—
Digital power supply pin (+3.3 V)
42
XI
I
X'tal 16.9344 MHz connect input
43
XO
O
X'tal 16.9344 MHz connect output
44
DGND
—
Digital ground pin
45
RFRPPFM
O
RFRP capacitor install pin or RF test monitor signal output
46
TZCRFM
O
TZC capacitor install pin or RF monitor signal output
47
SC
I
Scratch depth adjustment resistor connected pin
48
TEO
O
Tracking error signal output
30
CDX-V5800
Pin No.
Pin Name
I/O
Pin Description
49
TEN
I
Tracking error amplifier feedback signal input
50
CAGC
I
RFAGC capacitor install pin
51
RFI
I
RF signal input
52
EQO
O
RF equalizer signal output
31
CDX-V5800
• IC400 SPCA717A-HL211 (VIDEO SIGNAL PROCESSOR) (SERVO BOARD (2/2))
Pin No.
Pin Name
I/O
Pin Description
1
FSADJUST
—
Full-Scale adjust control pin The Full-Scale current of D/A converters can be
adjusted by connecting a resistor (RESET) between this pin and ground.
2
COMP
—
Compensation pin A0.1
µF ceramic capacitor must be used to bypass this pin to VAA.
The lead length must be kept as short as possible to avoid noise.
3
AVCC
—
Analog power supply pin (+3.3 V)
4
VREF OUT
O
Voltage reference signal output It generates typical 1.2 V voltage reference and may
be used to drive pin 5 (VREF IN) directly.
Voltage reference signal input An external voltage reference must supply typical
5
VREF IN
I
1.235 V to this pin. A0.1
µF ceramic capacitor must be used to de-couple this input
to ground. The decoupling capacitor must be as closed as possible to minimize the
length of the load. The pin may be connected derectry to pin 4 (VREF OUT).
6
VBIAS
—
DAC bias voltage Potential normally 0.7 V less than pin 2 (COMP).
7
NC
—
Not used. (Open)
8
AGND
—
Analog ground pin
Power save mode A logic high on this pin puts the chip into power-down mode. This
9
SLEEP
I
pin is equal to reset pin. An external logic high pulse should input to the pin when
power on.
10
SVIDEO
I
Video signal selection pin A logic high selects Y output. A logic low selects
composite video output. Not used in this set. (Fixed at “L”.)
11
CBSWAP
I
Cr and Cb pixel sequence configuration pin A logic high swap the Cr and Cb sequence.
Not used in this set. (Fixed at “L”.)
12
MASTER
I
Master/Slave mode selection A logical high for master mode operation. A logical 0
for slave mode operation. Not used in this set. (+3.3 V)
13
MODEA
I
Mode configuration pin Not used in this set. (Fixed at “L”.)
14
MODEB
I
Mode configuration pin
15
CLK
I
27 MHz crystal oscillator input A crystal with 27 MHz clock frequency can be
connected between this pin and pin qh (XTALO).
16
XTALO
O
Crystal oscillator output Not used in this set. (Open)
17 to 24
P0 to P7
I
YCrCb pixel inputs
They are latched on the rising edge of CLK.
25
CLKOUT
O
Pixel clock signal output Not used in this set. (Open)
26
DGND
—
Digital ground pin
27
VDD
—
Digital power supply pin (+3.3 V)
28
VSYNC
I/O
Vertical sync input/output
VSYNC is latched/output following the rising edge of CLK.
29
HSYNC
I/O
Horizontal sync input/output
HSYNC is latched/output following the rising edge of CLK.
30
TEST
I
Test pin These pins must be connected to digital ground.
31
AGND
—
Analog ground pin.
32
CVBSY
O
Composite/Luminance output. This is a high-impedance current source output. The
output format can be selected by the PAL pin. The CVBSY can drive a 37.5
Ω load.
32
CDX-V5800
• IC801 MB90477PF-G-185-BNDE1 (SYSTEM CONTROL) (MAIN BOARD (3/3))
Pin No.
Pin Name
I/O
Pin Description
1
LINE ATT
O
Audio mute control signal output
2 to 4
NC
—
Not used in this set. (Open)
5
BEEP
O
Beep signal output to power amp IC
6
VOL ATT
O
Electrical volume ATT control signal output
7 to 10
NC
—
Not used in this set. (Open)
11
VSS
—
Ground pin
12 to 14
NC
—
Not used in this set. (Open)
15
TU ATT
O
Tuner mute control signal output
16, 17
NC
—
Not used in this set. (Open)
18
CD SI
I
CD servo serial data signal input
19
CD SO
O
CD servo serial data signal output
20
CD SCK
O
CD servo serial clock signal output
21
RE 0
I
Rotary encoder signal input 0
22
RE 1
I
Rotary encoder signal input 1
23
VCC+3.3
—
Power supply pin (+3.3 V)
24
EEP SIO
I/O
Serial data signal input/output for EEPROM communication
25
EEP SCK
O
Serial clock signal output for EEPROM communication
26
SHUT SW
I
Shutter switch open/close detect signal input
“L”: Panel open, “H”: Panel close Not used in this set. (Open)
27
LCD CE
O
Chip enable signal output to LCD driver IC
28
LCD SO
O
Serial data signal output to LCD driver IC Flash: UART serial out
29
LCD SCK
O
Serial clock signal output to LCD driver IC
30
NC
—
Not used in this set. (Open)
31
STB
O
Standby signal output to power amp IC
32
AUX
—
Not used in this set. (Open)
33
IIC SCK
O
IIC bus serial clock signal output
34
IIC SIO
I/O
IIC bus serial data signal input/output
35
VCC+3.3
—
Power supply pin (+3.3 V) (for A/D converter)
36
AVRH+3.3
—
External reference power supply (+3.3 V) (for A/D converter)
37
AVSS
—
Ground pin (for A/D converter)
38, 39
KEY IN0, 1
I
Key signal input
40
NC
—
Not used in this set. (Open)
41
NC
—
Not used in this set. (Fixed at “H”.)
42
VSS
—
Ground pin
43, 44
NC
—
Not used in this set. (Fixed at “L”.)
45
VSM
I
S meter voltage detect signal input
46
DST SEL
I
Destination select pin
47
KEY ACK
I
Key acknowledge detect signal input
48
NC
—
Not used in this set. (Open)
49, 50
MD0, 1
I
Input for operation mode designation (Fixed at “H”.)
51
MD2
I
Input for operation mode designation (Fixed at “L”.)
52
NC
—
Not used in this set. (Open)
53
BU IN
I
Back up power supply detect signal input
54
SP
O
SP mode select signal output
55
CD SELFSW
I
CD mechanism self load position detect switch signal input
56
DIAG
I
Condition input from power amp IC
57
NC
—
Not used in this set. (Open)
58
UNI SI
I
Serial data signal input
59
UNI SO
O
Serial data signal output
60
UNI SCK
O
Serial clock signal output Not used in this set. (Open)
61
BUS ON
O
Bus on signal output
62
SYS RST
O
System reset signal output
Ver. 1.1
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