Sony CDX-V4800 Service Manual ▷ View online
29
CDX-V4800
• IC PIN DESCRIPTIONS
• IC500 BU9536KS2 (RF AMP, DIGITAL SERVO) (SERVO BOARD (1/2))
Pin No.
Pin Name
I/O
Pin Description
1
AVDD1
—
Analog power supply (+3.3 V)
2
AC
I
A+C voltage signal input from optical pick-up block
3
BD
I
B+D voltage signal input from optical pick-up block
4
VBIAS
O
Bias level (VDD/2) signal output
5
E
I
E voltage signal input from optical pick-up block
6
F
I
F voltage signal input from optical pick-up block
7
AGND1
—
Analog ground
8
FEN
I
Focus error amplifier feedback signal input
9
FEO
O
Focus error signal output
10
PKC
O
RF signal peak detection capacitance connected pin
11
BTC
O
RF signal bottom detection capacitance connected pin
12
PD
I
APC photo detector signal input
13
LD
O
APC laser drive signal output
14
PCO
O
PLL PCO signal output
15
FCO
O
PLL FCO-DAC signal output
16
ASY
I
Asymmetry revice and comparator slice capacitor install pin
17
JUMPO
O
Tracking jump pulse signal output
18
TDOUT
O
Tracking drive signal output
19
SDIN
I
Sled signal input
20
SDOUT
O
Sled drive signal output
21
FDOUT
O
Focus drive signal output
22
CLVOUT
O
CLV drive signal output
23
CLK88
—
Not used. (Open)
24
LON
O
Laser on control signal output
25
CLK
—
Not used. (Open)
26
MCK
I
Transfer clock signal input for sub Q and command data
27
DIN/DOUT
I/O
Command data signal input/status, sub-Q signal output
28
R/W
I
Read/write signal input for command data
29
RESETX
I
System reset signal input “L”: reset
30
BUSY
O
Busy signal output
31
SUBSYQ
O
Sub cord synchronizing signal output
32
SUBDATA
O
Sub cord data signal output
33
SUBCK
I
Sub cord bit clock signal input Not used in this set. (Fixed at “L”.)
34
WFCK
O
Disc frame synchronizing signal output
35
DOUTA
O
Audio serial data signal output
36
LRCK
O
Audio LR signal output
37
DCK
O
Audio serial bit clock signal output
38
EFLAG
I/O
Error flag signal input/output Not used in this set.
39
BUFO
—
Not used. (Open)
40
XPLCK
—
Not used. (Open)
41
DVDD
—
Digital power supply (+3.3 V)
42
XI
I
Main clock input (16.934 MHz)
43
XO
O
Main clock output (16.934 MHz)
44
DGND
—
Digital ground
45
RFRPPFM
O
RFRP capacitor install pin or RF test monitor signal output
46
TZCRFM
O
TZC capacitor install pin or RF monitor signal output
47
SC
I
Scratch depth adjustment resistor connected pin
48
TEO
O
Tracking error signal output
30
CDX-V4800
49
TEN
I
Tracking error amplifier feedback signal input
50
CAGC
I
RFAGC capacitor install pin
51
RFI
I
RF signal input
52
EQO
O
RF equalizer signal output
Pin No.
Pin Name
I/O
Pin Description
31
CDX-V4800
• IC400 SPCA717A-HL211 (D/A CONVERTER) (SERVO BOARD (2/2))
Pin No.
Pin Name
I/O
Pin Description
1
FSADJUST
—
Full-Scale adjust control pin The Full-Scale current of D/A converters can be
adjusted by connecting a resistor (RESET) between this pin and ground.
2
COMP
—
Compensation pin A0.1 µF ceramic capacitor must be used to bypass this pin
to VAA. The lead length must be kept as short as possible to avoid noise.
3
AVCC
—
Analog power supply (+3.3 V)
4
VREF_OUT
O
Voltage reference signal output It generates typical 1.2 V voltage reference
and may be used to drive pin 5 (VREF_IN) directly.
5
VREF_IN
I
Voltage reference signal input
The pin may be connected directory to pin 4 (VREF_OUT).
6
VBIAS
—
DAC bias voltage Potential normally 0.7 V less than pin 2 (COMP).
7
NC
—
Not used. (Open)
8
AGND
—
Analog ground
9
SLEEP
I
Power save mode A logic high on this pin puts the chip into power-down mode.
This pin is equal to reset pin. An external logic high pulse should input to the pin
when power on.
10
SVIDEO
I
Video signal selection pin A logic high selects Y output. A logic low selects
composite video output. Not used in this set. (Fixed at “L”.)
11
CBSWAP
I
Cr and Cb pixel sequence configuration pin A logic high swap the Cr and Cb
sequence. Not used in this set. (Fixed at “L”.)
12
MASTER
I
Master/Slave mode selection A logical high for master mode operation.
A logical 0 for slave mode operation. Not used in this set. (Fixed at “H”)
13
MODEA
I
Mode configuration pin Not used in this set. (Fixed at “L”.)
14
MODEB
I
Mode configuration pin
15
CLK
I
27 MHz clock input
16
XTALO
—
Not used. (Open)
17 to 24
P0 to P7
I
YCrCb pixel data signal inputs
25
CLKOUT
O
Pixel clock signal output Not used in this set. (Open)
26
DGND
—
Digital ground
27
VDD
—
Digital power supply (+3.3 V)
28
VSYNC
I/O
Vertical sync input/output
29
HSYNC
I/O
Horizontal sync input/output
30
TEST
I
Test pin Not used in this set. (Fixed at “L”.)
31
AGND
—
Analog ground
32
CVBS/Y
O
Composite/Luminance output. This is a high-impedance current source output.
The output format can be selected by the PAL pin.
32
CDX-V4800
• IC801 MB90488BPF-G-210E1 (SYSTEM CONTROL) (MAIN BOARD (3/3))
Pin No.
Pin Name
I/O
Pin Description
1
LINE_ATT
O
Audio mute control signal output
2 to 4
NC
—
Not used. (Open)
5
BEEP
O
Beep signal output
6
VOL_ ATT
O
Electrical volume ATT control signal output
7 to 10
NC
—
Not used. (Open)
11
VSS
—
Ground
12 to 14
NC
—
Not used. (Open)
15
TU_ATT
O
Tuner mute control signal output
16, 17
NC
—
Not used. (Open)
18
CD_SI
I
CD servo serial data signal input
19
CD_SO
O
CD servo serial data signal output
20
CD_SCK
O
CD servo serial clock signal output
21
RE 0
I
Rotary encoder signal input 0
22
RE 1
I
Rotary encoder signal input 1
23
VCC+3.3
—
Power supply (+3.3 V)
24
EEP_SIO
I/O
Serial data signal input/output for EEPROM communication
25
EEP_SCK
O
Serial clock signal output for EEPROM communication
26
SA_SCK
O
Spectrum analyzer clock output
27
LCD_CE
O
Chip enable signal output to LCD driver IC
28
LCD_SO
O
Serial data signal output to LCD driver IC
29
LCD_SCK
O
Serial clock signal output to LCD driver IC
30
NC
—
Not used. (Open)
31
STB
O
Standby signal output to power amp IC
32
NC
—
Not used. (Open)
33
IIC_SCK
O
IIC bus serial clock signal output
34
IIC_SIO
I/O
IIC bus serial data signal input/output
35
VCC+3.3
—
Power supply (+3.3 V) (for A/D converter)
36
AVRH+3.3
—
External reference power supply (+3.3 V) (for A/D converter)
37
AVSS
—
Ground
38, 39
KEY_IN0, 1
I
Key signal input
40
SA_DATA
I
Spectrum analyzer data signal input
41
NC
—
Not used. (Open)
42
VSS
—
Ground
43
NC
—
Not used. (Fixed at “L”.)
44
TU_QUAL
—
Not used. (Fixed at “L”.)
45
VSM
I
S meter voltage detect signal input
46
DST_SEL
I
AM tuner frequency step (9K/10K) select signal input
47
KEY_ACK
I
Key acknowledge detect signal input
48
NC
—
Not used. (Open)
49, 50
MD0, 1
I
Input for operation mode designation (Fixed at “H”.)
51
MD2
I
Input for operation mode designation (Fixed at “L”.)
52
OPEN MUTE
—
Not used. (Open)
53
BU_IN
I
Back up power supply detect signal input
54
SP
O
SP mode select signal output
55
CD_SELFSW
I
CD mechanism self load position detect switch signal input
56
DIAG
I
Condition input from power amp IC
57
NC
—
Not used. (Open)
58
UNI_SI
I
Serial data signal input
59
UNI_SO
O
Serial data signal output
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