Sony CDX-MP70 Service Manual ▷ View online
13
CDX-MP70
SECTION 3
PHASE ALIGNMENT
3-1. GEAR (CAM L)
3-2. GEAR (CAM R)
1
motor block assy
center mark
gear (cam L) position setting hole
2
PTT 2.6x6
gear (cam R) position setting hole
center mark
cam block assy
• Align the gear (cam L) position setting hole with the center mark on
the bracket before screwing the motor block assy to the mechanism
chassis.
chassis.
1
Align the gear (cam R) position setting hole with the center mark
on the bracket before screwing the cam block assy to the
mechanism chassis.
on the bracket before screwing the cam block assy to the
mechanism chassis.
2
Touch the gear (cam R) with fingers in the direction of rotation
and make sure that there is no phase difference with the R-side
position setting hole.
and make sure that there is no phase difference with the R-side
position setting hole.
14
CDX-MP70
4-1. IC PIN DESCRIPTIONS
• IC5 CXD9684R-004 (AUDIO INTERFACE) (SERVO BOARD)
Pin No.
Pin Name
I/O
Pin Description
1
RESET
I
Reset input
2
MIMD
I
CPU interface mode select signal
3
AD0
I
CPU interface chip select signal
4
AD1
I
CPU interface latch pulse signal
5
MIDIO
I/O
CPU interface data input/output
6
MICK
I
CPU interface clock signal
7
AD2/MIACK
I
CPU interface acknowledge signal
8
VDDT
—
Power supply pin (+3.3 V)
9
SDO
O
Data output
10
AD3/BCKO
O
Bit output
11
AD4/LRCKO
O
LR clock output
12
SDI0
I
Data input 0
13
BCKIA
I
Bit clock input A
14
LRCKIA
I
LR clock input A
15
AD5/SDI1
I
Data input 1
16
CE/BCKIB
I
Bit clock input B
17
OE/LRCKIB
I
LR clock input B
18
VDD
—
Power supply pin (+2.5 V)
19
STANDBY
I
Standby mode control signal
20
VSS
—
Ground
21
VSSL
—
Ground for DAC Lch
22
VRAL
—
Reference voltage pin for DAC Lch
23
LO
O
DAC Lch output
24
VDAL
—
Power supply pin (+2.5 V) for DAC Lch
25
VDAR
—
Power supply pin (+2.5 V) for DAC Rch
26
RO
O
DAC Rch output
27
VRAR
—
Reference voltage pin for DAC Rch
28
VSSR
—
Ground for DAC Rch
29
TESTP
I
Test pin
30
CKS
I
VCO select signal
31
AD12/PO0
O
Address output 0
32
AD11/PO1
O
Address output 1
33
AD10/PO2
O
Address output 2
34
AD9/PO3
O
Address output 3
35
VDDT
—
Power supply pin (+3.3 V)
36
AD8/PO4
O
Address output 4
37
AD7/PO5
O
Address output 5
38
AD6/PO6
O
Address output 6
39
PO7
O
Address output 7
40
VSS
—
Ground
41
AD13/FI0
I
Flag input 0
42
AD14/FI1
I
Flag input 1
43
WR/FI2
I
Flag input 2
44
AD16/FI3
I
Flag input 3
45
AD15/IRQ
I/O
External interrupt signal
46
IO0/PI0
I
Data input 0
47
IO1/PI1
I
Data input 1
48
VSS
—
Ground
49
IO2/PI2
I
Data input 2
50
IO3/PI3
I
Data input 3
51
IO4/PI4
I
Data input 4
SECTION 4
DIAGRAMS
15
CDX-MP70
Pin No.
Pin Name
I/O
Pin Description
52
VDD
—
Power supply pin (+2.5 V)
53
IO5/PI5
I
Data input 5
54
IO6/BOOT
I
Boot control signal
55
IO7/TXO
I
SPDIF signal
56
VSSP
—
Ground
57
PDO
O
PLL phase detect signal
58
VCOI
I
VCO control voltage input
59
VDDP
—
Power supply pin (+2.5 V) for VCO
60
CKI/ACKO
I/O
External clock input/audio clock output
61
VDDX
—
Power supply pin (+2.5 V) for crystal oscillator
62
X1
I
Crystal oscillator (16.934 MHz)
63
X0
O
Crystal oscillator (16.934 MHz)
64
VSSX
—
Ground
16
CDX-MP70
• IC11 HD6432238RWN13TEI (CD SYSTEM CONTROL) (SERVO BOARD)
Pin No.
Pin Name
I/O
Pin Description
1
TEST
I
Test mode select signal
2
DEC XRST
O
DEC reset output
3
DEC STBY
O
DEC standby mode control signal
4
XRDE
O
DRAM data read-out enable signal
5
(NCO)
O
Not used. (Open)
6
XWRE
O
DRAM write-in enable signal
7
SCLK
O
SENS read-out serial clock signal
8
SENS
I
SENS signal
9
CD CLK
O
CD servo serial clock signal
10
CD DAT
O
CD servo serial data output
11
CD LAT
O
CD servo latch signal
12
CVCC
—
Power supply pin (+3.3 V)
13
DAC MUTE
O
DAC mute control signal
14
VSS
—
Ground
15
MUTE
O
Audio mute control signal
16
XRST
O
CD servo reset signal
17
XQOK
O
CD servo sub-code Q OK signal
18
EMPH
O
Emphasis control signal
19
GFS
I
GFS signal
20
FOK
I
FOK signal
21
APC2
O
APC control signal 2
22
APC1
O
APC control signal 1
23
SPST
O
Spindle kick signal
24
RW SEL
O
Not used. (Open)
25
RF SW
O
Not used. (Open)
26
SIZE
I
Not used. (Open)
27
D IN
I
Not used. (Open)
28
D OUT
I
Not used. (Open)
29
LIM SW
I
PU inner detect SW signal
30
PSB
O
Mute signal
31
PC TX
O
Bus data output
32
PC RX
I
Bus data input
33
IN SW
I
Not used. (Open)
34
LM LO
O
Not used. (Open)
35
LM EJ
O
Not used. (Open)
36
EJECT OK
I
Front panel open mode signal
37
CLOSE OK
O
Not used. (Open)
38
SCOR
I
Sub-code sync detect signal
39
TRAY LAMP
O
Not used. (Open)
40
GRSCOR
I
DRAM controller sub-code sync detect signal
41
HSTX
O
High speed signal
42
AVSS
—
Ground
43
TE BAL ADJ
O
TE balance adjustment
44
DRAM
O
Not used. (Open)
45
D SW
I
Disc chucking detect signal
46
TRAY CUR
I
Tray current detect signal
47
KEY0
I
Test mode key SW input
48
KEY1
I
Test mode rotary SW input
49
(NCO)
I
Connecting to ground in this set.
50
(NCO)
I
Connecting to ground in this set.
51
TEMP
I
Tempareture detect signal
52
(NCO)
I
Connecting to ground in this set.
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