Sony CDX-MP30 Service Manual ▷ View online
13
13
CDX-MP30
SECTION 3
DIAGRAMS
3-1. Block Diagram –CD Section–
• R-ch is omitted due to
same as L-ch.
• Signal path
:CD
:CD-R/RW(MP3)
84
85
82
83
16
12
D/A
CONV
TRACKING
ERROR
FORCUS
ERROR
9
1
OSC
EFM
DEMOD
SERVO
CTL
RF
EQ
EQ
52
56
54
55
DSUB CODE
PROCESS
8
7
6
5
4
3
2
33
40
9
10
71
94
83
84
85
35
36
37
28
I/F
87
86
97
98
LD
DRIVE
Q1
FOCUS
COIL
DRIVE
TRACKING
COIL
DRIVE
SLED
MOTOR
DRIVE
SPINDLE
MOTOR
DRIVE
LOADING
MOTOR
DRIVE
6
5
23
2
15
16
17
18
13
14
11
12
9
10
26
62 63 64 65
17
18
59
Q913,914
CDM ON
SWITCH
SWITCH
Q915
CD ON
SWITCH
Q916,D927
CD+5V
REG
Q912,D926
CD DRIVE+6V
REG
M902
(SLED)
M901
(SPINDLE)
M903
(LOADING)
SW3
(DISC IN)
SW2
(SELF)
SW4
(LIMIT)
X1
16.9344MHz
X2
12.288MHz
OPTICAL PICK-UP
KSS-720A
I-V
CONV.
CDL
STB
AO
TSO
38 PACK
34 TSTB
TSI
27 FLAG
TSCK
CD_RST
RFOK
XTALEN
/RESET
STANDBY
REQ
MIDIO(I2C_SDA)
MICK(I2C_SCL)
X1
SDO
SDIO
BCKIA
LRCKIA
63 XTAL
65 EXTAL
INSW/PH2
11
SW1
(DOWN)
D_SW
SELF SW
LIMIT_SW
LOAD
EJECT
CDMON
CDON
R-CH
MAIN
SECTION
A
A-ATT
MAIN
SECTION
B
23
24
M
M
M
BATT
D925
LOUT
ROUT
PACK
TSTB
TSI
TSCK
SI
RFOK
FLAG
C16M
DIN
DECXRST
DECSTBY
DECINT
SDA
SCL
DOUT
SCKIN
SCKO
LRCKIN
LRCK
SO
SCK
STB
AO
XTALEN
RST
RSTX
92
BUCHK
91
BUSON
78
UNI CK
77
UNI_SI
76
UNI_SO
75
LINKOFF
BU CHK
BUSON
BUS-CLK
BUS-SI
BUS-SO
LINK-OFF
93
A-ATT
A
C
B
D
E
F
PD
LD
B
D
A
C
E
F
PD
A+5V
LD
APC
FCS-
FCS+
TRK+
TRK-
SL-
SL+
SP+
SP-
LD-
LD+
FOCUS
COIL
TRACKING
COIL
FD
TD
SD
MD
LOAD
EJECT
IC3
CD MASTER CONTROL
IC1
RF AMP,DIGITAL SERVO
DIGITAL SIGNAL PROCESSOR
IC2
FOCUS/TRACKING COIL DRIVE,
SLED/SPINDLE/LOADING MOTOR DRIVE
FD
TD
SD
MD
A+5V
AU+5V
D+5V
DR+6V
38
28
29
30
31
32
33
34
62
9
12
13
14
2
3
72
8
1
19
39
5
81
6
4
1
2
IC12
IC5
DSP
IC7
5V 3.3V
17
3
14
12
7
16
18
6
8
13
4
2
5
15
9
11
SYSRST
MAIN
SECTION
C
MAIN
SECTION
D
21-23
25-29
25-29
20-13
3,2,31
1,12,4
1,12,4
11,7,10
46,47
49-51
53-55
49-51
53-55
3,4
7,10
11,15
38-36
34-31
41,42
45,44
38-36
34-31
41,42
45,44
32
30
5
16
17
43
OE
CS1
OE
CE
CE
WR
WR
IO0-IO7
DQ1-DQ3,
IO4-IO8
AD0-AD16
A0-A16
IC4
S-RAM
+2.5V
(IC5)
BU+3.3V
3
+2.5V
REG
2
IC6
Ver 1.1 2002.06
14
14
CDX-MP30
3-2. Block Diagram –MAIN Section–
• R-ch is omitted due to same as L-ch.
• Signal path
:FM
:AM(MW/LW)
:CD
:CD-R/RW(MP3)
PJ601
(ANTENNA)
2
10
1
ANT-FM
MPX
CDL
8
AM DET
14
S-METER
12
SDA
13
SCL
17
SDA(EEP)
18
9
SCL(EEP)
RDS DET
ANT-AM
TU601
TUNER UNIT
2
45
47
70
14
15
20
21
18
11
13
1
3
30
IC801 (1/2)
SYSTEM CONTROL
IC402
INPUT SELECTOR,
ELECTRONIC VOLUME,
SIGNAL PROCESSOR
AUX L
OUT LF
29
OUT LR
28
OUT RF
27
OUT RR
35
BEEP
ATT
67
69
AMP ON
66
AMP ATT
40
TEL ATT
38
ACC IN
CD L
MPX
R-CH
AM
LEVEL
MPIN
SDA
SCL
MUTE
17 QUAL
VOL ATT
7 QUALITY
90 NS_MASK
VSM
I2C SIO
I2C CKO
EE SIO
EE CKO
MPTH(DSTSEL)
DAVN(NIL)
AUDIO OUT REAR
CD
SECTION
A
CD
SECTION
B
CD
SECTION
C
CD
SECTION
D
Q904,905
LINE MUTE
SWITCH
Q402
MUTE
R-CH
Q401
MUTE
22 MUTE
4 STBY
16 AUX
11
12
5
3
9
7
IC401
POWER AMP
1
-1
-2
-5
-6
-3
-4
9
2
10
CNP901
R-CH
PJ401
FL+
FL-
RL+
RL-
4
12
FR+
FR-
3
11
RR+
RR-
16 +B (BATT)
13 ATT
5 AMP R
6
8
19
ANT R
GND
R-CH
BATT
F900
10A
Q901
TEL
ATT
ATT
Q911,D918,919
TUNER +5V
REG
Q601
BUFFER
Q909,910
TUNER ON
SWITCH
Q906,D917
+8V REG
Q907,908
POWER ON
CONTROL
Q921
AMP REM
CONTROL
CONTROL
SWITCH
Q920
AMP B+
SWITCH
Q917
ANT REM
CONTROL
SWITCH
Q922
ANT B+
SWITCH
7 ACC
15 TEST
49
50
TUN ON
37
TEST IN
Q902
ACC
DETECT
PW ON
24
SYSRST
25
BUSON
43
BUSSI
44
BUSCKO
42
BUSSO
28
BU IN
87
86
BATT
Q801,D801,802
BATT DET
Q804
BUS-SO
SWITCH
Q805,806
LIMNKOFF
SWITCH
Q802
SWITCH
BATT
Q903,D916
+5V REG
BATT
BU+5V
BU+3.3V
+8V
TUNER
+8V
TUNER
+5V
BATT
17
18
L
R
AUDIO OUT FRONT
R-CH
L
R
BUS AUDIO IN
R-CH
L
R
CDR
R-CH
2 CD R
IC601
RDS DECODER
IC803
BUS INTERFACE
8
27
13 RST
12 BUSON
8 DATA OUT
11 CLK IN
9 DATA IN
10 B/U-C
6
DATA I/O
4
CLK
2
RST
3
BATT
8
7
5
6
4
2
3
1
BATT
CNJ801
BUS
CONTROL IN
IC602
NOISE AMP
Q602
NS MASK
SWITCH
X601
4.332MHz
DELAY
BATT
D921,922
1
BUSON
33
1
RESET
S801
RESET
2
IC802
3
+3.3V
REG
2
IC902
BU+5V
RESET
16 MPX
4 OSCO
5 OSCI
LVIN
SDA
SCL
20
9
10
MPTH 2
DAVN 8
D601
5
7 2
1
SYSRST
D810
D806
D818
A-ATT
D701
D819
IC701
BUFFER
BU-CHECK
BUSON
BUS-SI
BUS-CLK
BUS-SO
LINK-OFF
2
6
5
3
7
1
AEP
AEP
15
15
CDX-MP30
3-3. Block Diagram –DISPLAY Section–
• Circuit Boards Location
Q803
KEY
DETECT
CNP801
(REMOTE IN)
IC552
X802
32.768kHz
15
16
12
13
5
18
20
19
4
26
91
98
6
29
2
IC801 (2/2)
SYSTEM CONTROL
IC501
LCD DRIVER
KEY IN0
DATA
CLK
CE
LCDSO
LCDCKO
LCDCE
Q919
ILL ON
SWITCH
Q918
ILL B+
SWITCH
KEY IN1
KEY ACK
XKEYON
RC IN1
RC IN0
SIRCS
XIN
XOUT
OSC OUT
93
ILLON
BATT
ILL B+
OSC IN
X801
18.432MHz
LED549,550
LCD BACK
LIGHT
64
63
62
COM1
COM4
LCD501
LIQUID
CRYSTAL
DISPLAY
D809
D807
(
)
D561-589
KEY
ILLUMINATION
(
)
52
|
55
2
I
13
•
15
|
38
•
40
I
51
S2
I
S48
|
REMOTE
CONTROL
RECEIVER
S501 -510
FUNCTION SWITCH
S511 -521
FUNCTION SWITCH
g
MAIN board
tuner unit
(TU601)
(TU601)
DISPLAY board
LOAD-SW board
SERVO board
DISC IN SW board
SPEAKER board
LIMIT SW board
• Waveforms
— SERVO Board —
(MODE: CD PLAY)
—
MAIN Board
—
1
IC1
wd
(XTAL)
2
IC1
uj
(RFO)
3
IC1
oa
(FEO)
4
IC1
od
(TEO)
4.8 Vp-p
59 ns
1V/DIV,20ns/DIV
5
IC3
yd
(XTAL)
2.7 Vp-p
82 ns
1V/DIV,40ns/DIV
Approx. 200m Vp-p
Approx. 300m Vp-p
100mV/DIV,20
µ
s/DIV
100mV/DIV,20
µ
s/DIV
500mV/DIV,1
µ
s/DIV
1.7 Vp-p
6
IC601
4
(OSCD)
7
IC801
qs
(OSCOUT)
8
IC801
qh
(XOUT)
2V/DIV,40ns/DIV
5.3 Vp-p
54 ns
2V/DIV,20
µ
s/DIV
5.4 Vp-p
30.5
µ
s
2V/DIV,100ns/DIV
230 ns
5.7 Vp-p
Ver 1.1 2002.06
16
16
CDX-MP30
3-4. Printed Wiring Boards –CD Section– • Refer to page 15 for Circuit Boards Location.
THIS NOTE IS COMMON FOR PRINTED WIRING
BOARDS AND SCHEMATIC DIAGRAMS.
(In addition to this, the necessary note is
printed in each block.)
BOARDS AND SCHEMATIC DIAGRAMS.
(In addition to this, the necessary note is
printed in each block.)
for schematic diagram:
• All capacitors are in
• All capacitors are in
µ
F unless otherwise noted. pF:
µµ
F
50 WV or less are not indicated except for electrolytics
and tantalums.
and tantalums.
• All resistors are in
Ω
and
1
/
4
W or less unless otherwise
specified.
•
%
: indicates tolerance.
•
f
: internal component.
•
C
: panel designation.
•
A
: B+ Line.
• Power voltage is dc 14.4V and fed with regulated dc power
supply from ACC and BATT cords.
• Voltages are taken with a VOM (Input impedance 10 M
Ω
).
Voltage variations may be noted due to normal produc-
tion tolerances.
tion tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal produc-
tion tolerances.
tion tolerances.
• Circled numbers refer to waveforms.
• Signal path.
F
: FM
f
: AM(MW/LW)
J
: CD
c
: CD-R/RW(MP3)
for printed wiring boards:
• X
: parts extracted from the component side.
• Y
: parts extracted from the conductor side.
•
x
: parts mounted on the conductor side.
•
a
: Through hole.
•
: Pattern from the side which enables seeing.
(The other layer’s patterns are not indicated.)
Caution:
Pattern face side: Parts on the pattern face side seen from the
(Side B)
Pattern face side: Parts on the pattern face side seen from the
(Side B)
pattern face are indicated.
Parts face side:
Parts on the parts face side seen from the
(Side A)
parts face are indicated.
Note: The components identified by mark
0
or dotted line
with mark
0
are critical for safety.
Replace only with part number specified.
IC6
IC12
C77
C79
FB6
C102
C78
Ref. No.
Location
IC6
B-4
IC12
B-3
Q1
A-1
• Semiconductor
Location
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