Sony CDX-M730 Service Manual ▷ View online
25
CDX-M730
• IC301 HD6432355A44F (SUB SYSTEM CONTROL)
Pin No.
Pin Name
I/O
Pin Description
1
SA CLK
O
Spectrum analyzer clock signal output to electronic volume (IC305)
2
NCO
O
Not used. (Open)
3
VSS
—
Ground pin
4
NC
—
Not used. (Open)
5
VCC
—
Power supply pin (+5 V)
6 to 9
NCO
O
Not used. (Open)
10
VSS
—
Ground pin
11 to 18
NCO
O
Not used. (Open)
19
VSS
—
Ground pin
20 to 27
NCO
O
Not used. (Open)
28
VSS
—
Ground pin
29 to 31
NCO
O
Not used. (Open)
32
SA EN
I
Spectrum analyzer enable signal input from system control (IC801)
33
NCO
O
Not used. (Open)
34
BU IN
I
Back-up voltage detect signal input from bus interface (IC802)
35, 36
VSS
—
Ground pin
37
NCO
O
Not used. (Open)
38
BUS ON
I
BUS ON signal input from system control (IC801)
39
VCC
—
Power supply pin (+5 V)
40 to 43
NCO
O
Not used. (Open)
44
VSS
—
Ground pin
45
NCO
O
Not used.
46
LED SW1
I
Illumination select control 1 signal input from system control (IC801)
47
LED SW2
I
Illumination select control 2 signal input from system control (IC801)
48, 49
NCO
O
Not used. (Open)
50
LINK OFF
O
LINK OFF signal output
51
NCO
O
Not used. (Open)
52
ILL ON
O
Illumination control signal output
53
VSS
—
Ground pin
54 to 56
NCO
O
Not used. (Open)
57
BOOT
I
Display CPU write-in control signal input from system control (IC801)
58
VCC
—
Power supply pin (+5 V)
59
NCO
O
Not used. (Open)
60
TX/LCD SO
O
LCD data output/UART signal output
61
NCO
O
Not used.
62
RX
I
UART signal input
63
NCO
O
Not used.
64
LCD CKO
O
LCD clock signal output to LCD driver (IC1, 60 and 61)
65
VSS
—
Ground pin
66
LCD CE0
O
LCD driver chip enable 1 signal output to LCD driver (IC60)
67, 68
VSS
—
Ground pin
69
LCD INH
O
LCD driver inhibit signal output to LCD driver (IC1, 60 and 61)
70
LCD CE1
O
LCD driver chip enable 2 output to LCD driver (IC61)
71
LCD CE2
O
LCD driver chip enable 3 output to LCD driver (IC1)
72 to 78
NCO
O
Not used. (Open)
79
FL W
O
Not used. (Open)
80
VCL
I
Connecting to ground through a capacitor. Not used in this set. (Open)
81
RES
I
Reset signal input
82
NMI (H)
I
Non maskable interrupt signal input
83
ST/SY (H)
I
Stanby mode signal input
84
VCC
—
Power supply pin (+5 V)
85
XTAL
—
Crystal oscillator (18.43 MHz)
26
CDX-M730
Pin No.
Pin Name
I/O
Pin Description
86
EXTAL
—
Crystal oscillator (18.43 MHz)
87
VSS
—
Ground pin
88
PF7
O
Not used. (Open)
89
VCC
—
Power supply pin (+5 V)
90 to 96
NCO
O
Not used. (Open)
97
UNI SO
O
Bus data signal output to bus interface (IC802)
98
UNI SI
I
Bus data signal input from bus interface (IC802)
99
VSS
—
Ground pin
100
VSS
—
Ground pin
101
UNI SCK
I
Bus clock signal input from system control (IC801)
102
P53
O
Not used. (Open)
103
AVCC
—
Power supply pin (+5 V)
104
VREF
—
Reference voltage (+5 V)
105 to 111
NIL
I
Connect to ground in this set.
112
SA IN
I
SA data signal input from electronic volume (IC305)
113
AVSS
—
Ground pin
114
VSS
—
Ground pin
115 to 122
NCO
O
Not used. (Open)
123
MD0 (H)
—
Mode pin
124
MD1 (H)
—
Mode pin
125
MD2 (H)
—
Mode pin
126 to 128
NCO
O
Not used. (Open)
27
27
CDX-M730
82
83
84
85
16
12
D/A
CONV
TRACKING
ERROR
FORCUS
ERROR
9
1
OSC
EFM
DEMOD
SERVO
CTL
RF
EQ
EQ
52
56
54
55
DSUB CODE
PROCESS
8
7
6
5
4
3
2
22
35
23
20
76
26
25
27
7
3
1
28
I/F
87
86
97
98
LD
DRIVE
Q1
FOCUS
COIL
DRIVE
TRACKING
COIL
DRIVE
SLED
MOTOR
DRIVE
SPINDLE
MOTOR
DRIVE
LOADING
MOTOR
DRIVE
6
5
23
2
15
16
17
18
13
14
11
12
9
10
26
62 63 64 65
59
58
CD POWER
CONTROL
Q913-915
Q913-915
M902
(SLED)
M901
(SPINDLE)
M903
(LOADING)
SW3
(DISC IN)
SW2
(SELF)
SW4
(LIMIT)
SW5
(DOWN)
X1
16.9344MHz
OPTICAL PICK-UP
KSS-720A
I-V
CONV.
CDL
STB
AO
CD_TSO
78 CD_PACK
29 TSTB
CD TSI
CD TCK
CD_RST
RFOK
9 XTALEN
D SW
IN/PH2
SELFSW
LIMIT
LOAD
EJECT
CD ON
R-CH
TUNER
SECTION
A
23
24
M
M
M
BATT
LOUT
ROUT
PACK
TSTB
TSI
TSCK
SI
RFOK
SO
SCK
STB
AO
XTALEN
RST
A
C
B
D
E
F
PD
LD
A
C
B
D
E
F
PD
A+5V
LD
APC
FCS-
FCS+
TRK+
TRK-
SL-
SL+
SP-
SP+
LD-
LD+
FOCUS
COIL
TRACKING
COIL
FD
TD
SD
MD
LOAD
EJECT
SYSTEM CONTROL
IC801 (1/3)
RF AMP,DIGITAL SERVO
DIGITAL SIGNAL PROCESSOR
IC1
FOCUS/TRACKING COIL DRIVE,
SLED/SPINDLE/LOADING MOTOR DRIVE
IC2
FD
TD
SD
MD
• Signal path
:CD
• R-ch is omitted due to
same as L-ch.
A+5V
AU+5V
D+5V
CD POWER
CONTROL
Q929,930
CD+6V
DR+6V
4-2. BLOCK DIAGRAM — CD SECTION —
(Page 28)
28
28
CDX-M730
4-3. BLOCK DIAGRAM — TUNER SECTION —
AJ1
(ANTENNA)
1
10
2
ANT AM
MPX
CDL
SAOUT
SACLK
8
AMDET
9
RDS
ANT FM
TUNER UNIT
TU601
FM AMP
Q607
NOISE
CANCEL
IC602
Q605
12
9
14
13
19
20
16
17
31
50
56
1
5
SYSTEM CONTROL
IC801 (2/3)
16
20
+5V
REG
IC905
1
2
14
S METER
VSM
NS MASK
52 MPTH
75 DAVN
75 DAVN
QUALITY
VOL ATT
SM
QUAL
SCL
SDA
LEVEL
MP IN
AM
MPX1
33 AC INL
38 AC OUTL
23 SA OUT
21 SACLK
12
SDA
70 I2CSIO
13
SCL
71 I2CCKO
17
SDA
10 E2PSIO
18
SCL
11 E2PCKO
4
FM AGC
51 FM AGC
RDS DECODER
IC601
FM DET
XO
XI
S METER
4
5
X601
4.3MHz
9
SDA
SCL 10
MPTH 2
DAVN 8
4
28
AUXL
OUT LF
43 MDL
ELECTRONIC VOLUME
IC305
27
OUT LR
23
OUT LR
55
AMP ON
5
ATT
16
TEL ATT
95
ILL IN
81
ACC IN
73
X1A
74
X0A
84
TEST IN
83
PW ON
92
X0
93
X1
114
TUN ON
CD
SECTION
A
DISPLAY
SECTION
SECTION
B
IC409
Q202
Q201
Q403
Q410
MUTE
CONTROL
Q401,402
12
5
3
11
22
4
9
7
POWER AMP
IC903
MUTE
STBY
CNP901
FL+
FL–
RL+
RL–
TEL MUTE
ILL
ACC
TEST
FR+
13
14
7
15
4
10
2
9
1
12
3
11
COM +8V
FR–
RR+
RR–
5
AMP REM
6
ANT REM
19
17
18
16
B+
B+
X802
32.768kHz
X801
3.68MHz
ILLUM CHECK
Q902
POWER
CONT
Q461
ACC CHECK
Q918
POWER
CONT
Q905,919
Q923
R-CH
BATT
BATT
+9V
TU +8V
POWER
CONT
Q924,925
+9V
BACKUP+6V
PULLUP+5V
Q917
Q901
PJ402
PJ401
–1
–2
R
L
SUB OUT (MONO)
–3
–4
R
L
AUDIO OUT
REAR
R-CH
–5
–6
R
L
AUDIO OUT
FRONT
R-CH
–1
–2
R
L
BUS AUDIO IN
R-CH
53
FL
RL
F901
• Signal path
: FM
: AM/MW
: CD
EEPROM
BATT
3
1
IC311
3
1
• R-ch is omitted due to
same as L-ch.
AEP,UK,E MODEL
D912
D905,914
(Page 27)
(Page 29)
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