Sony CDX-M610 Service Manual ▷ View online
21
CDX-M610
3-3. MOTOR BLOCK
3-4. ALIGNMENT BETWEEN ARM (A-L) ASSY
AND ARM (B-L) ASSY
AND ARM (B-L) ASSY
1
Turn the cam (L) and position the cam so that part
A
does not touch the SWITCH board SW900.
1
Input 9V DC to the motor terminal until the cam (L)
stops rotating.
Take care to avoid overload of the motor.
stops rotating.
Take care to avoid overload of the motor.
2
Verify that the arm (A-L) assy and arm (B-L) assy
are positioned as shown below (full open).
3
PTT 2.6x6
4
PTT 2.6x6
2
motor block
SWITCH board
SW900
cam (L)
5
screw (+BTT)
A
motor
GND
arm (B-L) assy
arm (A-L) assy
DC 9V
+B
22
CDX-M610
3-6. CAM (R)
3-5. ARM (A-R) ASSY, ARM (B-R) ASSY
1
Move the arm (B-R) assy in the direction of the
arrow
arrow
A
and the arm (A-R) assy in the direction of
the arrow
B
fully (full open state).
2
Align the hole on the cam (R) with part
C
and install
the cam.
4
Turn the cam (R) clockwise and counterclockwise to
verify that both the arms are operated.
verify that both the arms are operated.
bracket (R) assy
4
arm (A-R) assy
3
spring (arm R)
2
stop ring 1.5, type-E
5
stop ring 1.5, type-E
1
arm (B-R) assy
3
stop ring 1.5, type-E
cam (R)
B
A
C
arm (B-R) assy
hole
arm (A-R) assy
23
CDX-M610
4-1. IC PIN DESCRIPTIONS
• IC501 CXD2598Q (DIGITAL SERVO, DIGITAL SIGNAL PROCESSOR) (SERVO BOARD)
Pin No.
Pin Name
I/O
Pin Description
1
DVDD
—
Digital power supply pin
2
DVSS
—
Digital ground
3
SOUT
O
Servo brock serial data output (Not used.)
4
SOCK
O
Servo brock serial data read clock output (Not used.)
5
XOLT
O
Servo brock serial data latch output (Not used.)
6
SQSO
O
Sub Q 80 bit, PCM peak and level data output. CD TEXT data output
7
SQCK
I
Clock input from SQSO read output.
8
SCSY
I
Fixed at “L”.
9
SBSO
O
Serial output of sub-P to W. (Not used.)
10
EXCK
I
Clock input from SBSO read output. (Fixed at “L”)
11
XRST
I
System reset (“L”: Reset)
12
STSM
I
System mute input (Fixed at “L”)
13
DATA
I
Serial data input from CPU.
14
XLAT
I
Latch input from CPU. Latch serial data at the falling edge.
15
CLOK
I
Serial data transfer clock input from CPU.
16
SENS
O
SENS output for CPU.
17
SCLK
I
Clock input from SENS serial data read.
18
ATSK
I/O
Input/output for anti-shock.
19
WFCK
O
WFCK (Write Flame Clock) output (Not used.)
20
XUGF
O
XUGF output (Not used.)
21
XPCK
O
XPCK output (Not used.)
22
GFS
O
GFS output
23
C2PO
O
C2PO output (Not used.)
24
SCOR
O
“H” output at either detection, sub code sync S0 or S1.
25
C4M
O
4.2336 MHz output (Not used.)
26
WDCK
O
Word clock input f=2Fs (Not used.)
27
COUT
I/O
Track number count signal input/output (Not used.)
28
MIRR
I/O
Mirror signal input/output (Not used.)
29
DVSS
—
Digital ground
30
DVDD
—
Digital power supply pin
31
DFCT
I/O
Diffect signal input/output (Not used.)
32
FOK
I/O
Focus OK signal output
33
PWM1
I
External control input of spindle motor.
34
LOCK
I/O
Lock signal input/output
35
MDP
O
Servo control output of spindle motor.
36
SSTP
I
Disc most inner track detection signal input
37
FSTIO
I/O
2/3 frequency division output of pins ih and ij. (Not used.)
38
SFDR
O
Sled drive output
39
SRDR
O
Sled drive output
40
TFDR
O
Tracking drive output
41
TRDR
O
Tracking drive output
42
FFDR
O
Focus drive output
43
FRDR
O
Focus drive output
44
DVDD
—
Digital power supply pin
45
DVSS
—
Digital ground
46
TEST
I
Test pin (Fixed at “L”.)
47
TES1
I
Test pin (Fixed at “L”.)
48
XTSL
I
X’tal select input (“L”: 16.9344 MHz, “H”: 33.8688 MHz)
49
VC
I
Center voltage input
50
FE
I
Focus error signal input
51
SE
I
Sled error signal input
SECTION 4
DIAGRAMS
24
CDX-M610
Pin No.
Pin Name
I/O
Pin Description
52
TE
I
Tracking error signal input
53
CE
I
Center servo analog input
54
RFDC
I
RF signal input
55
ADIO
O
Test pin (Not used.)
56
AVSSO
—
Analog ground
57
IGEN
I
Constant current input from OP amplifier.
58
AVDDO
—
Analog ground
59
ASYO
O
EFM full-swing output (“L”: VSS, “H”: VDD)
60
ASYI
I
Asymmetry comparate voltage input
61
RFAC
I
EFM signal input
62
AVSS3
—
Analog ground
63
CLTV
I
VCO control voltage input from master.
64
FILO
O
Filter output for master PLL. (slave=digital PLL)
65
FILI
I
Filter input from master PLL.
66
PCO
O
Charge pump output for master PLL.
67
AVDD3
—
Analog power supply pin
68
BIAS
I
Asymmetry circuit constant current input
69
VCTL
I
VCO2 control input from wideband EFM PLL.
70
V16M
O
VCO2 oscillator output for wideband EFM PLL. (Not used.)
71
VPCO
O
Charge pump output for wideband EFM PLL. (Not used.)
72
DVSS
—
Digital ground
73
MD2
I
Digital out ON/OFF control input (“L”: OFF, “H”: ON)
74
DOUT
O
Digital out output
75
ASYE
I
Asymmetry circuit ON/OFF input (“L”: OFF, “H”: ON)
76
DVDD
—
Digital power supply pin
77
LRCK
O
D/A interface LR clock output (f=Fs)
78
LRCKI
I
D/A interface LR clock input
79
PCMD
O
D/A interface serial data output (2’s COMP, MSB fast)
80
PCMD
I
D/A interface serial data input (2’s COMP, MSB fast)
81
BCK
O
D/A interface bit clock output
82
BCKI
I
D/A interface bit clock input
83
EMPH
O
Emphasis ON/OFF signal output
84
EMPHI
I
Emphasis ON/OFF signal input (“H”: ON, “L”: OFF)
85
XVDD
—
Power supply for master clock.
86
XTAI
I
X’tal oscillator input from master clock (16.9344 MHz).
87
XTAO
O
X’tal oscillator output for master clock (16.9344 MHz).
88
XVSS
—
Ground pin for master clock.
89
AVDD1
—
Analog power supply pin
90
AOUT1
O
Lch analog output
91
AIN1
I
Lch OP amplifier input
92
LOUT1
O
Lch LINE output
93
AVSS1
—
Analog ground
94
AVSS2
—
Analog ground
95
LOUT2
O
Rch LINE output
96
AIN2
I
Rch OP amplifier input
97
AOUT2
O
Rch analog output
98
AVDD2
—
Analog power supply pin
99
RMUT
O
Rch “0” detect Flug (Not used.)
100
LMUT
O
Lch “0” detect Flug (Not used.)
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