Sony CDX-H905IP / CDX-HR905IP Service Manual ▷ View online
CDX-H905IP/HR905IP
29
• IC Block Diagrams
IC300 TDA8588AJ/N2/R1 (MAIN Board (1/4))
IC601 BA8271F-E2 (MAIN Board (1/4))
MUTE
MUTE
ENABLE
LOGIC
STANDBY/
MUTE
BATTERY
DETECTION
CHIP DETECT/
DIAGNOSTIC
PROTECTION/
DIAGNOSTIC
SWITCH
REGULA
TOR
SWITCH
REFERENCE
VOLTAGE
LOADDUMP
PROTECTION
TEMPERATURE
PROTECTION
BACK-UP
SWITCH
REGULATOR
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
TAB
LF–
LF+
LR–
LR+
IN-RL
S-GND
IN_LF
RR+
RR–
RF+
RF–
DIAG
SW2
SW1
REG3
REG4
VP
REG2
SDA
SCL
VP2
PGND3
SVR
IN_RR
IN_LR
ACGND
PGND2
VP1
STB
PGND1
RST
CRES
REG1
GND
REG5
CBU
FL
RL
RR
VP
FR
I
2
C BUS
1
2
3
4
5
6
5
6
7
8
9
10
14
13
12
11
12
11
BUS ON
SWITCH
RESET
SWITCH
BATTERY
SWITCH
BUS.ON
RST
BATT
CLK
VREF
GND
VCC
RST
BUS.IN
CLK-IN
B/U-C
BUS.IN
CLK-IN
B/U-C
DATA IN
DATA OUT
DATA I/O
CDX-H905IP/HR905IP
30
IC401 BD3442FS-E2 (MAIN Board (2/4))
IC50 TDA7333013TR (MAIN Board (2/4)) (CDX-HR905IP only)
1
2
A1
100k
100k
100k
100k
100k
100k
250k
250k
250k
A2
B1 3
4
B2
5
C1
6
C2
7
DP1
8
DN
9
DP2
10
DS32
11
DS12
12
DS22
13
EBIAS
14
DS21
15
DS11
16
DS31
26 OUTF1
27 VCC
VCC
VCC2
28 MUTE
29 SCL
30 SDA
31 GND
32 FIL
INPUT
SELECTOR
VOLUME1
/MUTE
VOLUME2
I2C
BUS
LOGIC
TREBLE
/BASS
/MIDDLE
SPECTRUM
ANALYZER
FADER
25 OUTF2
24 OUTR1
23 OUTR2
FADER
FADER
22 OUTS1
21
20
OUTS2
19
ADJ
18
SOUT
17
DATA
CLK
FADER
FADER
LPF
EFFECT
INPUT
GAIN
FADER
VDDA
INTERPOLATOR
RAM
BUFFER
&
CONTROL
LOGIC
TEST LOGIC
&
PIN MUX'S
I
2
C/SPI
INTERFACE
BAND PASS
FILTER
SIGMA DELTA
CONVERTER
SINC4
FILTER
REF3
REF2
REF1
VSS
VDDD
RESETN
TM
1
MPX
16
CSN
SDAOUT
RDSREG
3
INTN
MPX
SINC4REG
SDAIN
SCK
SCK
SPI
TESTREG
TESTREG
14
2
3
4
5
6
7
8
INTN
15
SA
13
SDA
12
SCL
11
OSCILLATOR
XTO
10
XTI
9
RDS
DEMODULATOR &
SYNCHRONIZATION
2
CDX-H905IP/HR905IP
31
IC800 NJM2387ADL3(TE2) (MAIN Board (3/4))
1
2
3
4
5
CURRENT
LIMIT
THERMAL
PROTECTION
OVERVOLTAGE
PROTECTION
BANDGAP
REFERENCE
VIN
CONT
VOUT
VADJ
GND
CDX-H905IP/HR905IP
32
IC250 ATMEGA32L-8AU-S6 (IPOD Board)
PROGRAM
COUNTER
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
PROGRAM
FLASH
STACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTERS
ALU
AVR CPU
Z
Y
X
EEPROM
OSCILLATOR
ADC
INTERFACE
TIMERS
/COUNTERS
OSCILLATOR
TWI
MCU CTRL.
& TIMING
INTERNAL
CALIBRATED
OSCILLATOR
OSCILLATOR
STATUS
REGISTER
PROGRAMMING
LOGIC
PORT B
DIGITAL
DIGITAL
INTERFACE
PORT B
DRIVERS
/BUFFERS
40
41
42
43
44
34
ADC3
ADC4
ADC5
ADC6
ADC7
AREF
GND
AV
C
C
TO
SC
2
TO
SC
1
TDI
TDO
MOSI
MISO
SCK
RESET
VCC
GND
XT
AL2
XT
AL1
RXD
TXD
INT
O
ADC2
ADC1
ADC0
VCC
GND
XCK/T0
T1
AIN0/INT2
AIN1/OC0
SS
TMC
TCK
SDA
SCL
OC2
ICP1
VCC
GND
INT1
OC1A
OC1B
30
31
32
33
35
36
36
37
38
39
2
1
3
4
5
9
10
11
7
8
6
INTERRUPT
UNIT
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
PORT A
DIGITAL
INTERFACE
PORT A
DRIVERS
/BUFFERS
PORT C
DRIVERS
/BUFFERS
22
25
26
27
28
29
23
24
21
20
20
19
13
12
14
15
16
17
18
PORT C
DIGITAL
DIGITAL
INTERFACE
PORT D
DIGITAL
DIGITAL
INTERFACE
PORT D
DRIVERS
/BUFFERS
COMP.
INTERFACE
USART
SPI
MUX &
ADC
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