Sony CDX-GT40U / CDX-GT40UW / CDX-GT42UE / CDX-GT44U / CDX-GT45U / CDX-GT47UE Service Manual ▷ View online
CDX-GT40U/GT40UW/GT42UE/GT44U/GT45U/GT47UE
37
• IC Pin Function Description
MAIN BOARD (2/5) IC501 R5F3650KBDZ78FA (SYSTEM CONTROL) (Former type)
MAIN BOARD (2/5) IC501 R5F3650KBDZ75FA (SYSTEM CONTROL) (New type)
MAIN BOARD (2/5) IC501 R5F3650KBDZ75FA (SYSTEM CONTROL) (New type)
Pin No.
Pin Name
I/O
Description
1
LCD_SO
O
Serial data output for LCD driver
2
LCD_CLK
O
Serial clock signal output for LCD driver
3
NOSE_SW
I
Front panel detach/attach detect input “L”: With panel, “H”: Without panel
4
SIRCS
I
Remote control signal (infrared) input
5
UNISO
O
SONY BUS serial data output
6
UNISI
I
SONY BUS serial data input
7
UNISCK
O
SONY BUS serial clock signal output
8
BYTE
I
External data bus width select signal input (Connect to VSS in this set)
9
CNVSS
I
Flash writer IF (CNVSS) signal input (L: normally operation, H: fl ash write)
10
XIN
I
Low speed operation clock signal input (32.768 kHz)
11
XOUT
O
Low speed operation clock signal output (32.768 kHz)
12
RESET
I
System reset signal input
13
OSCOUT
O
High speed operation clock signal output (7.92 MHz)
14
VSS
―
Ground terminal
15
OSCIN
I
High speed operation clock signal input (7.92 MHz)
16
VCC1
―
Power supply terminal (+3.3 V)
17
NMI
I
Non-maskable interrupt signal input (Fixed at H in this set)
18
RC_IN1
I
Rotary commander shift key signal input
19
BUIN
I
Backup power supply detect signal input
20
SYSRST
O
System reset signal output
21
BUS_ON
O
VBUS power control signal output
22
MC_RX
I
MC-BUS communication MECHA (MG-101CA) TX signal input
23
DOOR_SW
O
Not used. (Open)
24
MC_TX
O
MC-BUS communication MECHA (MG-101CA) RX signal output
25
DOOR_ING
O
Not used. (Open)
26
SYNC_OUT
O
DD converter frequency control signal output
27
EJECT_OK
O
Not used. (Open)
28
BEEP
O
Beep signal output for the power amplifi er IC
29
I2C_SCL
O
IIC communication serial clock signal output
30
I2C_SDA
I/O
IIC communication serial data input/output
31
FW_TXD
O
Flash writer IF (serial data) output
32
FW_RXD
I
Flash writer IF (serial data) input
33
FW_CLK
I
Flash writer IF (serial clock) signal input
34
FW_BUSY
O
Flash writer IF (busy) signal output
35
XM_TX
O
Not used. (Open)
36
XM_RX
O
Not used.
37
XM_POWER EN
O
Not used.
38
CD_ON
I
CD mechanism servo power supply control request signal input
39
CDM_ON
I
CD mechanism deck power supply control request signal input
40
WAKE_UP
O
CD mechanism deck micon wake up signal output
41
EPM
O
EPM signal output (Fixed at L in this set)
42
Z_MUTE
I
Z mute signal input
43
R/S SW_SEL
O
Not used. (Open)
44
EQ_TYPE__SEL
O
Not used. (Open)
45
INITCOL_SEL
O
Not used. (Open)
46
CE
O
CE signal output (Fixed at H in this set)
47
HIT2_SDA
I/O
Tuner serial data input/output
48
HIT2_SCL
O
Tuner serial clock output
49
HIT2_RESET
O
Tuner reset signal output
50
EN_USB
O
USB over current detect IC control signal output
51
VBUS_ON
I
VBUS power supply control signal input (L: VBUS OFF, H: VBUS ON)
52
FLT_USB
I
USB over current detect signal input
53
EN_SYS
O
Power control DC/DC signal output
54
IPOD
O
iPod connection mode signal output
Ver. 1.3
Note: Refer to “ABOUT CHANGE OF THE LCD DRIVER IC (IC901)
ON THE KEY BOARD” on page 7 for New/Former types of IC501.
CDX-GT40U/GT40UW/GT42UE/GT44U/GT45U/GT47UE
38
Pin No.
Pin Name
I/O
Description
55
EXTATT_XEN
O
External mute control signal output
“L”: CD or USB source is selected, “H”: Other source is selected
“L”: CD or USB source is selected, “H”: Other source is selected
56
TELATT
I
Telephone attenuator detect signal input (Fixed at L in this set)
57
ACC_IN
I
Accessory power supply detect signal input
58
ATT
O
Audio mute control signal output
59
DIAG
I
Condition signal input from power amp IC
60
AMPSTB
O
Standby signal output for power regulator IC
61
CYRIL_SEL
I
Cyril correspondance discrimination signal input (L: No correspondance) (Fixed at L in this
set)
set)
62
VCC2
―
Power supply terminal (+3.3 V)
63
F_AUX_ATT
O
Not used. (Open)
64
VSS
―
Ground terminal
65
ILLUMI SEL
I
Key illumination voltage setting signal input Not used. (Open)
66
COLSW SEL
I
Key illumination color change function signal input Not used. (Open)
67
BT_MUTE
O
Not used. (Open)
68
B-OUT SEL
I
Black out function setting signal input (L: without black out function) Not used. (Open)
69
AREASEL3
I
Destination setting pin 3 Not used. (Open)
70
AREASEL2
I
Destination setting pin 2 Not used. (Open)
71
AREASEL1
I
Destination setting pin 1 Not used. (Open)
72
AREASEL0
I
Destination setting pin 0 Not used. (Open)
73
MODELNAME_SEL0
O
Not used. (Open)
74
MODELNAME_SEL1
O
Not used. (Open)
75
MODELNAME_SEL2
O
Not used. (Open)
76
MODELNAME_SEL3
O
Not used. (Open)
77
BT_TX
O
Not used. (Open)
78
BT_RX
O
Not used. (Open)
79, 80
DEBUG_1, DEBUG_2
O
Not used. (Open)
81
RE-IN1
I
Rotary encoder signal input 1
82
RE-IN0
I
Rotary encoder signal input 0
83
ILL_IN
O
Not used. (Open)
84
BT_RTS
O
Not used. (Open)
85
BT_CTS
O
Not used. (Open)
86
BT_RESET
O
Not used. (Open)
87
BT_POWER
O
Not used. (Open)
88
BT_MIC_DET
O
Not used. (Open)
89
SA_DATA
I
Mechnism serial data input
90
SA_CLK
O
Mechnism serial clock output
91
KEYACK0
I
Key acknowledge detect signal input (Rotary commander)
92
KEYACK1
I
Key acknowledge detect signal input (Front panel)
93
BT_MIC_ON
O
Not used. (Open)
94
KEYIN1
I
Key signal input 1
95
KEYIN0
I
Key signal input 0
96
AVSS
―
Ground terminal for A/D converter
97
RC_IN0
I
Rotary commander key signal input
98
AVRH
―
A/D converter external reference power supply terminal (+3.3 V)
99
AVDD
―
A/D converter power supply terminal (+3.3 V)
100
LCD_CE
O
Chip enable signal output for LCD driver
CDX-GT40U/GT40UW/GT42UE/GT44U/GT45U/GT47UE
39
MAIN BOARD (4/5) IC701 TC94A99FG-003 (SY) (DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
LPFO
O
Signal output from the operation amplifi er for PLL loop fi lter
2
PVREF
I
Reference voltage (+1.65V) input terminal
3
VCOF
O
Terminal for VCO fi lter
4
RVSS3
―
Ground terminal
5
VCOI
I
DSP VCO control voltage input terminal
6
RVDD3
―
Power supply terminal (+3.3V)
7
SLCO
O
EFM slice level output terminal
8
RFI
I
RF signal input terminal
9
RFRPI
I
RF ripple signal input terminal
10
RFEQO
O
EFM slice level output terminal
11
DCOFC
O
DCOFC signal output
12
AGCI
I
RF signal amplitude adjustment amplifi cation input terminal
13
RFO
O
RF signal generation amplifi cation output terminal
14
RVSS3
―
Ground terminal
15
FNI2
I
Main beam input terminal (Connect with pin diode C)
16
FNI1
I
Main beam input terminal (Connect with pin diode A)
17
FPI2
I
Main beam input terminal (Connect with pin diode D)
18
FPI1
I
Main beam input terminal (Connect with pin diode B)
19
VDD1-1
―
Power supply terminal (+1.5V)
20
TPI
I
Sub beam amplifi cation input terminal (Connect with pin diode F)
21
TNI
I
Sub beam amplifi cation input terminal (Connect with pin diode E)
22
VRO
O
Reference voltage (+1.65V) output terminal
23
AVSS3
―
Ground terminal
24
MDI
I
Monitor photo diode amplifi cation input terminal
25
LDO
O
Laser diode amplifi cation output terminal
26
FSMONIT
―
Not used. (Open)
27
RFZI
I
RF ripple zero crossing signal input terminal
28
RFRP
O
RF ripple signal output terminal
29
TEI
I
Tracking error signal input terminal
30
AVDD3
―
Power supply terminal (+3.3V)
31
FOO
O
Focus servo equalizer signal output terminal
32
TRO
O
Tracking servo equalizer signal output terminal
33
VSS-1
―
Ground terminal
34
FMO
O
Feeding servo equalizer signal output terminal
35
DMO
O
Disc servo equalizer signal output terminal
36
VDDM1
―
Power supply terminal (+1.5V)
37
/SRAMSTB
I
Strobe signal input from the USB controller “L”: standby mode
38
VDD1-2
―
Power supply terminal (+1.5V)
39
VDD3-1
―
Power supply terminal (+3.3V)
40
CD-MON2/PIO10
―
Not used. (Open)
41
CD-MON3/PIO11
―
Not used. (Open)
42
PIO12/DT/BT_DATAi
―
Not used. (Open)
43
PIO13/DT/BT_BCKi
―
Not used. (Open)
44
PIO14/DT/BT_LRCKi
―
Not used. (Open)
45 to 47
PIO15/SDo0 to
PIO17/SDo2
―
Not used. (Open)
48
PIO18/LRCKo
―
Not used. (Open)
49
PIO19/BCKo
―
Not used. (Open)
50
PIO20/CKo
―
Not used. (Open)
51
DVDD12
―
Power supply terminal (+3.3V)
52
DAO1 (R_R-CH)
O
R_R channel data output terminal
53
DVSS12
―
Ground terminal
54
DAO2 (F_R-CH)
O
F_R channel data output terminal
55
DVREF
―
Reference voltage input terminal
56
DVDD34
―
Power supply terminal (+3.3V)
57
DAO3 (F_L-CH)
O
F_L channel data output terminal
58
DVSS34
―
Ground terminal
59
DAO4 (R_L-CH)
O
R_L channel data output terminal
60
DVDD5
―
Power supply terminal (+3.3V)
CDX-GT40U/GT40UW/GT42UE/GT44U/GT45U/GT47UE
40
Pin No.
Pin Name
I/O
Description
61
DAO5 (SUB-CH)
O
SUB channel data output terminal
62
DVSS5
―
Ground terminal
63
VDD1-3
―
Power supply terminal (+1.5V)
64
VSS-2
―
Ground terminal
65
XVSS3
―
Ground terminal
66
XI
I
System clock input terminal (16.9344 MHz)
67
XO
O
System clock output terminal (16.9344 MHz)
68
XVDD3
―
Power supply terminal (+3.3V)
69
ADVDD3
―
Power supply terminal (+3.3V)
70
ADIN1 (IN_L-CH)
I
Audio signal input terminal (L channel)
71
ADVREFL
O
Reference voltage output terminal
72
ADVCM
O
Reference voltage output terminal
73
ADVREFH
O
Reference voltage output terminal
74
ADIN2 (IN_R-CH)
I
Audio signal input terminal (R channel)
75
ADVSS3
―
Ground terminal
76
MS
I
I/F mode selection signal input terminal Fixed at “L” in this set
77
BUS0
I/O
Bus data input/output with the USB controller
78
BUS1
I/O
Bus data input/output with the USB controller
79
BUS2/So
O
Serial data output to the USB controller
80
BUS3/Si
I
Serial data input from the USB controller
81
BUCK/SCL
I
Bus clock signal input from the USB controller
82
/CCE
I
Chip enable signal input from the USB controller
83
VDD3-2
―
Power supply terminal (+3.3V)
84
VSS-3
―
Ground terminal
85
/RST
I
Reset signal input from the system controller
86
VDD1-4
―
Power supply terminal (+1.5V)
87
DEC_REQ
O
Request signal output to the USB controller
88
BSIF-REQ
O
Request signal output to the USB controller
89
BSIF-GATE
I
Gate signal input from the USB controller
90
BSIF_DATA
I
Audio data input from the USB controller
91
BSIF_BCK
I
Bit clock signal input from the USB controller
92
BSIF_LRCK
I
L/R sampling clock signal (44.1 kHz) input terminal for audio data input
93
DEC_XMUTE
I
Muting on/off control signal input from the USB controller
94
ZDET
O
Zero detection signal output terminal
95
CD MON0/SP_DATA
O
Spectrum analyzer data output to the USB controller
96
CD MON1/SP_CLK
I
Spectrum analyzer data transfer clock signal input from the USB controller
97
TEST
I
Setting terminal for test mode Normally fi xed at “L”
98
PDO
O
Phase error margin signal between EFM signal and PLCK signal output terminal
99
TMAX
O
TMAX detection result output terminal
100
LPFN
I
Inverted signal input from the operation amplifi er for PLL loop fi lter
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