Sony CDX-F5550 Service Manual ▷ View online
13
13
CDX-F5550
CDX-F5550
87
RFO
RF AMP,DIGITAL SERVO,
DIGITAL SIGNAL PROCESSOR
IC2
79
RFEQO
3
RFRP
6
TEI
77 RFI
78 RFRPI
78 RFRPI
1 RFZI
7 TEZI
9 F0O
PD1
PD2
E
F
I-V AMP
PD
LD
DETECTOR
85 AGCI
86 RFDCI
86 RFDCI
94
96
95
97
99
98
TNI
FPI1
FNI1
FPI2
FNI2
TPI
91 LDO
92
MDI
(FOCUS)
(TRACKING)
2-AXIS DEVICE
OPTICAL
PICK-UP BLOCK
(KSS1000E)
• Signal Path
: CD PLAY
LASER DIODE
M
M
M
18
17
VO3–
VO3+
14
13
VO1+
VO1–
12
11 VO2–
VO2+
10
9
VOL+
VOL–
FWD
REV
1
28
OPIN4– 26
OPOUT4 25
10 TRO
OPIN3– 23
46 IO0(/HSO)
OPOUT3 22
12 FMO
OPOUT1 4
13 DMO
OPIN2 7
47 IO1(/UHSO)
MUTE 21
16
15
VO4–
VO4+
M903
(LOADING)
M901
(SPINDLE)
M902
(SLED)
FOCUS/TRACKING COIL DRIVE,
SLED/SPINDLE/LOADING
MOTOR DRIVE
IC1
56
MUTE
53
REQ
43
STBY
18
ZDET
42
/RST
41
/CCE
40
BUCK
39
BUS3
CD-L
MAIN
SECTION
A
30
LO
27
RO
R-CH
27 DEC SSTBY
15 CD ZDET
15 CD ZDET
14 CD XRST
13 CD XCCE
53 MEC_SELFSW
45 MEC_INSW
42 MEC_LIMIT
12 CD BUCK
11 CD BUS3
38
BUS2
10 CD BUS2
37
BUS1
8
CD BUS1
36
BUS0
7
CD BUS0
14
SBSY
52 CD SBSY
81 X1
80 X0
MEC LOAD
43
MEC EJECT
44
CD
SYSTEM CONTROL
IC3
+1.5V REG
IC6
SYSTEM CONTROL
IC501 (1/3)
37 DEC XMUTE
30 DEC INT
SW2
(SELF)
46 MEC_DSW
SW1
(DOWN)
SW3
(DISC IN)
SW4
(LIMIT)
56
UNISI
25
RXD
57
UNISO
58
UNICKI
50
BUS ON
51
BU IN
75
RSTX
61
EJECT OK
67
MECON CHK
1
DECON
63
MECON
64
CDON
66
ZMUTE
60
A ATT
26
TXD
PD1
E
F
LD
MON OUT
FCS+
FCS–
TRK+
TRK–
PD2
LD DRIVE
Q1
+1.5V ON/OFF
SWITCH
Q2,3
• R-ch is omitted due to same as L-ch.
24
23
X2
16.934MHz
X1
12MHz
XI
XO
MAIN
SECTION
B
EJECT OK SW
UNI SI
UNI SO
A-ATT
UNI CLK
BUS ON
B/U CHECK
SYS RST
89
CD ON
VOUT
98
CDM ON
99
Z MUTE
MECHA+6V
93
68
CDON CHK
1
5
VDD
3
CE
BU+3.3V
+1.5V
+1.5V
BU+3.3V
59
LINK OFF
LINK OFF
3-1. BLOCK DIAGRAM — CD SECTION —
SECTION 3
DIAGRAMS
(Page 14)
(Page 14)
14
14
CDX-F5550
CDX-F5550
J1
(ANTENNA)
1 ANT
CDL
CDR
CD-L
TU-L
R-CH
3
R
AUDIO 8.3V
TUNER UNIT
TU1
6
S-METER
14
SDA
SYSTEM CONTROL
IC501 (2/3)
86
ACCIN 72
TELATT 74
AMPSTB 26
BEEP 5
CD
SECTION
A
CD
SECTION
B
3
11
CN300
J451
1
9
FL+
FL-
2
10
RL+
RL-
4
12
13
7
FR+
FR-
15
RR+
RR-
TEST
ACC
ATT
16 +B (BATT)
8 GND
R-CH
FU601
10A
TU_ATT
BU3.3V
17
19
18
BATT
BATT
EEP_CKO
25
VSM
BU3.3V
13
SCL
ATT
BATT
D493
8
TESTIN
DIAG
73
39
5
QUALITY
QUALITY
38
NS-MASK
13
VOLATT
9
DAVN
56
RDS ON
30
BUS-LCH
DIFFL
11
SE1L
9
SE2L
7
SDA
SCL
MUTE
CONT.
EVR
21
I2C_SIO
I2C_CKO
34
33
17
E2P-SDA
16
E2P-SCL
8
MUTE CON
7
TUN MUTE
11
VDD5V
10
VCC8.3V
24 EEP_SIO
12
TU_ATTIN
53
R-CH
9
RDS OUT
16 MPX
9 XTI
10
1
7
XTO
12
SDA
25
29
AUDIO OUT FRONT
L
R
R-CH
5 AMP-R
27
35
37
34
33
31
30
6 ANT-R
BEEP
STB
FL
RL
SUB-L
4
SCL
2
SDA
CONT.
9
7
6
20
POWER AMP
IC300 (1/2)
POWER SUPPLY
IC300 (2/2)
VP2
VP1
VP1
• Signal path
: FM
: MW
: CD
• R-ch is omitted due to same as L-ch.
AUDIO OUT REAR
L
R
R-CH
BUS AUDIO IN
L
R
R-CH
12
BUIN
A-ATT
54
UNI SCK 60
4
L
OUTLF
20
OUTLR1
19
SYSRST 88
RESET 77
+5V REG.
Q3
RESET
IC602
LINE MUTE
CONTROL
Q491,492
TEL
ATT
ATT
Q701
I2C
BUS
ACC
CHECK
Q702
MUTE
Q440
NS MASK
SWITCH
Q1
MUTE
Q470
11
MUTE
TONE
INPUT SELECTOR
EFFECT
15
INTN
11
SCL
OUTLR2
16
MUTE
Q430
5
3
DIAG
AMP-REM
ANT-REM
B.UP+B
PANEL+B
MECH 6V
SERVO 3.3V
AUDIO +B
BU5V
PANEL+B
MECH 6V
SERVO 3.3V
AUDIO 8.3V
SERVO 3.3V
AUDIO 8.3V
VP
D302
D301
D603
D602
D400
D511
S103
RESET
BUS INTERFACE
IC601
MUTE
16
22
I2C
BUS
23
22
RDS POWER
CONTROL
Q50
RDS DECODER
IC50
X50
8.664MHz
UNI SI
UNI SO
UNI CLK
BUS ON
LINK OFF
B/U CHECK
SYS RST
B/U C
10
RST
13
DATA IN
9
CLK IN
11
BUS IN
12
DATA OUT
8
1
2
BU5V
BU3.3V
+3.3V REG
IC502
3
2
UNI SI 58
UNI SO 59
BUS ON 87
BATT 3
RST 2
DATA I/O 6
4
5
6
5
6
1
7
8
2
3
3
CLK 4
BUS ON 1
BATTERY
CHECK
Q605
LINK
SWITCH
Q600,601
CNJ400
(BUS CONTROL IN)
ELECTRONIC VOLUME
IC401
3-2. BLOCK DIAGRAM — MAIN SECTION —
(Page 13)
(Page 13)
15
15
CDX-F5550
CDX-F5550
3-3. BLOCK DIAGRAM — DISPLAY SECTION —
S801
S901-907,
910-923
S901-907,
910-923
KEY ON
SWITCH
Q501
IR RECEIVER
IC971
X501
32.768kHz
79
80
83
82
41
28
29
27
40
52
76
71
43
64
83
SYSTEM CONTROL
IC501 (3/3)
LCD DRIVER
IC901
KEYIN0
DATA
CLK
CE
LCDSO
LCDCKO
LCDCE
KEYIN1
KEYACK
XKEYON
RCIN1
RCIN0
SIRCS
OUT
XIN
7 NOSE DET
XOUT
OSCOUT
OSCIN
46
DOOR IND
X500
18.432MHz
77
78
76
COM1
COM4
LCD
LCD901
PANEL +B
LED901-907,
910-923
910-923
LED801
(DOOR IND)
LED802
( Z )
D501
J370
(REMOTE IN)
65
|
68
|
S1
S62
|
DI
CL
CE
1 DIMMER
S102
(NOSE DET)
KEY
ILLUMINATION
(
)
PANEL +B
LED961,962
(LCD BACK LIGHT)
KEY MATRIX
DIMMER
CONTROL
Q961
LED DRIVE
Q589,590
3-30
33-64
69,74
69,74
16
16
CDX-F5550
CDX-F5550
• NOTE FOR PRINTED WIRING BOARDS AND SCHEMATIC DIAGRAMS
3-4. CIRCUIT BOARDS LOCATION
• WAVEFORMS
— MAIN BOARD —
— SERVO BOARD —
(CD PLAY)
THIS NOTE IS COMMON FOR PRINTED WIRING
BOARDS AND SCHEMATIC DIAGRAMS.
(In addition to this, the necessary note is printed
in each block.)
BOARDS AND SCHEMATIC DIAGRAMS.
(In addition to this, the necessary note is printed
in each block.)
For schematic diagrams.
Note:
• All capacitors are in
• All capacitors are in
µ
F unless otherwise noted. (p: pF)
50 WV or less are not indicated except for electrolytics
and tantalums.
and tantalums.
• All resistors are in
Ω
and
1
/
4
W or less unless otherwise
specified.
•
f
: internal component.
•
C
: panel designation.
For printed wiring boards.
Note:
• X
: parts extracted from the component side.
• Y
: parts extracted from the conductor side.
•
a
: Through hole.
•
: Pattern from the side which enables seeing.
(The other layers' patterns are not indicated.)
•
A
: B+ Line.
•
B
: B– Line.
•
H
: adjustment for repair.
• Voltages and waveforms are dc with respect to ground
under no-signal (detuned) conditions.
• CD mechanism section (1/2), (2/2)
no mark : CD PLAY
• Main (1/2), (2/2), Key and Display sections
no mark : FM
no mark : CD PLAY
• Main (1/2), (2/2), Key and Display sections
no mark : FM
(
) : MW/LW
<
> : CD PLAY
∗
: Impossible to measure
• Voltages are taken with a VOM (Input impedance 10 M
Ω
).
Voltage variations may be noted due to normal produc-
tion tolerances.
tion tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal produc-
tion tolerances.
tion tolerances.
• Circled numbers refer to waveforms.
• Signal path.
J
: CD PLAY
F
: FM
f
: MW/LW
Caution:
Pattern face side: Parts on the pattern face side seen from the
(Side B)
Pattern face side: Parts on the pattern face side seen from the
(Side B)
pattern face are indicated.
Parts face side: Parts on the parts face side seen from the
(Side A)
(Side A)
parts face are indicated.
Q
C
These are omitted
E
B
E
These are omitted
C
B
C
These are omitted
B
E
1
IC2
4
(FEI)
Approx.
1 Vp-p
1 Vp-p
0 V
0.6 Vp-p
16.9344 MHz
Approx. 100 mVp-p
50 mV/DIV, 5 msec/DIV
0.5 V/DIV, 0.5
µ
sec/DIV
2
IC2
6
(TEI)
200 mV/DIV, 5 msec/DIV
6
IC2
oh
(FPI2),
0.5 V/DIV, 0.5
µ
sec/DIV
Approx. 400 mVp-p
3
IC2
wd
(XI)
0.2 V/DIV, 0.2
µ
sec/DIV
7
IC3
ia
(X1)
0.5 V/DIV, 0.2
µ
sec/DIV
1.1 Vp-p
12 MHz
4
IC2
uj
(RFI)
0.5 V/DIV, 0.5
µ
sec/DIV
5
IC2
of
(FNI2),
og
(FNI1)
1.5 Vp-p
oj
(FPI1)
1.5 Vp-p
0 V
4.5 Vp-p
8.664 MHz
1
IC50
0
(XTO)
0.5 V/DIV, 0.2
µ
sec/DIV
5 Vp-p
32.768 kHz
2
IC501
i;
(XOUT)
0.2 V/DIV, 20
µ
sec/DIV
4.8 Vp-p
18.432 MHz
3
IC501
id
(OSCOUT)
0.5 V/DIV, 0.1
µ
sec/DIV
MAIN board
SUB board
KEY board
SENSOR board
SERVO board
tuner unit
(TU1)
(TU1)
Note: The components identified by mark
0
or dotted line
with mark
0
are critical for safety.
Replace only with part number specified.
Click on the first or last page to see other CDX-F5550 service manuals if exist.