Sony CDX-C8850R Service Manual ▷ View online
29
Pin No.
Pin Name
I/O
Pin Description
60
BU.IN
I
Back-up power detection input
61
BUSON
I
Bus on control input
62
IN SW
I
Disc in switch input (SW1)
63
SELF SW
I
Self switch input (SW2)
64
TX CE
O
EEPROM chip enable output
65
SCK2
O
Sub Q read clock output
66
SI2
I
Sub Q 80 bit, PCM peak and level data 16 bit input
67
CD DATA
O
CD signal process serial data output
68
ESPXWRE
O
Write signal output to DRAM controller.
69
ESPXRDE
O
Read signal output to DRAM controller.
70
ESPXLT
O
Serial data latch output to DRAM controller.
71
ESPXSOE
O
XSOE signal output to DRAM controller.
72
VDD
—
Power supply
73
HIN
I
Fixed at “H” in this set.
74
TEXT.ON/OFF
I
Fixed at “H” in this set.
75
PH1
I
Not used in this set.
76
FBTBSEL
I
Not used in this set.
77
CDOSEL
I
Not used in this set.
78 – 80
—
—
Not used in this set.
30
• IC300 CXD2727Q (DIGITAL SIGNAL PROCESSOR) (MAIN BOARD)
Pin No.
Pin Name
I/O
Pin Description
1
VSS1
—
Digital ground
2 – 15
TD0 – 13
I
Test pin (Normally, fixed at “L”.)
16 – 21
TST0 – 5
I
Test pin (Normally, fixed at “L”.)
22 – 24
JPE1 – 3
I
External condition jump input (“H” : condition jump) (Fixed at “L” in this set.)
25
VDD1
—
Digital power supply pin (+3.3 V)
26
AVS3
—
Analog ground (for D/A converter 1)
27
FL-OUT
O
Analog signal output for front (L-ch) output.
28
AVD3
—
Analog power supply pin (+3.3 V) (for D/A converter 1)
29
RL-OUT
O
Analog signal output for rear (L-ch) output.
30
AVD5
—
Analog power supply pin (+3.3 V) (for D/A converter 1)
31
AVS5
—
Analog ground (for D/A converter 1)
32
AVD1
—
Analog power supply pin (+3.3 V) (for A/D converter L-ch)
33
AVS1
—
Analog ground (for A/D converter L-ch)
34
LREF
O
Pass control connection pin for A/D converter. (for L-ch)
35
LIN
I
Tuner and bus audio in signal input (for L-ch)
36
AVS7
—
Analog ground (for D/A converter 2)
37
AVD7
—
Analog power supply pin (+3.3 V) (for D/A converter 2)
38
NCO
—
Not used. (Open)
39
AVDX
—
Analog power supply pin (+3.3 V) (for master clock)
40
XTLO38
O
System clock output (16.9344 MHz)
41
XTLI38
I
System clock input (16.9344 MHz)
42
AVSX
—
Analog ground (for master clock)
43
SUB-OUT
O
Analog signal output for sub woofer output.
44
AVD8
—
Analog power supply pin (+3.3 V) (for D/A converter 2)
45
AVS8
—
Analog ground (for D/A converter 2)
46
RIN
I
Tuner and bus audio in signal input (for R-ch)
47
RREF
O
Pass control connection pin for A/D converter. (for R-ch)
48
AVS2
—
Analog ground (for A/D converter R-ch)
49
AVD2
—
Analog power supply pin (+3.3 V) (for A/D converter R-ch)
50
AVS6
—
Analog ground (for D/A converter 3)
51
AVD6
—
Analog power supply pin (+3.3 V) (for D/A converter 3)
52
RR-OUT
O
Analog signal output for rear (R-ch) output.
53
AVD4
—
Analog power supply pin (+3.3 V) (for D/A converter 3)
54
FR-OUT
O
Analog signal output for front (R-ch) output.
55
AVS4
—
Analog ground (for D/A converter 3)
56
VSS2
—
Digital ground
57
RST
I
System reset signal input from system control (IC500). (“L” : reset)
58
BFOT
O
Master clock output for CD.
59
SCK
I
Clock signal input for serial data transfer from system control (IC500).
60
REDY
O
Micon interface transfer permission signal output to system control (IC500).
(“L” : transfer prohibit)
61
TRDT
O
Serial data output to system control (IC500).
62
LAT
I
Serial data latch pulse input from system control (IC500).
63
RVDT
I
Serial data input from system control (IC500).
64
XS24
I
Serial data 24/32 bit slot select signal input from system control (IC500).
(“L” : 24 bit slot, “H” : 32 bit slot) (Valid at slave mode.)
65
VDD2
—
Digital power supply pin (+3.3 V)
66
VSS3
—
Digital ground
67 – 69
SO1 – 3
O
Serial data output (Not used in this set.)
70
SOUT
O
Serial data output (Not used in this set.)
71
SI1
I
Serial data input
72, 73
SI2, 3
I
Serial data input (Fixed at “L” in this set.)
31
Pin No.
Pin Name
I/O
Pin Description
74
SIN
I
Serial data input (Fixed at “L” in this set.)
75
BCK
I
Clock signal input for serial bit transfer of serial input/output data.
76
LRCK
I
Sampling frequency clock signal input of serial input/output data.
77
XMST
I
Bit clock (BCK) and L/R sampling clock (LRCK) signal master/slave mode select
signal input from system control (IC500). (“L” : master mode, “H” : slave mode)
78
VDD3
—
Digital power supply pin (+3.3 V)
79
AVSP
—
PLL system ground
80
PLLEN
I
PLL enable signal input (Normally, fixed at “L”.)
81
PLCLK
O
PLL clock signal output (Not used in this set.)
82
CKSTP
I
PLL clock output control signal input from system control (IC500).
83
AVDP
—
PLL system power supply pin (+3.3 V)
84
VSS4
—
Digital ground
85 – 94
TD14 – 23
I
Test pin (Normally, fixed at “L”.)
95
VDD4
—
Digital power supply pin (+3.3 V)
96
AVSD
—
Ground (for D-RAM)
97
SCLI
I
Not used. (Normally, fixed at “L”.)
98
BIM
I
Not used. (Normally, fixed at “L”.)
99
SDRAM
I
Not used. (Normally, fixed at “L”.)
100
AVDD
—
Power supply pin (+3.3 V) (for D-RAM)
32
• IC701 HD6432355A08F (DISPLAY CONTROL) (MAIN BOARD)
Pin No.
Pin Name
I/O
Pin Description
1, 2
PG3, 4
O
Not used. (Open)
3
VSS
—
Ground
4
NC
—
Not used. (Open)
5
VCC
—
Power supply pin (+5 V)
6 – 9
PC0 – 3
O
Not used. (Open)
10
VSS
—
Ground
11 – 14
PC4 – 7
O
Not used. (Open)
15 – 18
PB0 – 3
O
Not used. (Open)
19
VSS
—
Ground
20 – 23
PB4 – 7
O
Not used. (Open)
24 – 27
PA0 – 3
O
Not used. (Open)
28
VSS
—
Ground
29
PA4/IRQ4
O
Not used. (Open)
30
PA5/IRQ5
O
Not used. (Open)
31
PA6/IRQ6
O
Not used. (Open)
32
PA7/IRQ7
O
Not used. (Open)
33
SP-LAT
I
Digital signal processor spectrum analyzer data latch input
34
P66/IRQ2
O
Not used. (Open)
35, 36
VSS
—
Ground
37
P65/IRQ1
O
Not used. (Open)
38
BUS-ON
I
SONY BUS ON input
39
VCC
—
Power supply pin (+5 V)
40
CD/MD
I
CD/MD mechanism deck setting input (“L” : CD mechanism deck)
41 – 43
PE1 – 3
O
Not used. (Open)
44
VSS
—
Ground
45
TIR IND
O
TIR indicator LED drive output
46, 47
PE5, 6
O
Not used. (Open)
48
MD LOCK
I
MD lock signal input (“L” : unlock)
49
BU-IN
I
Back-up power supply detection input
50
LINK-OFF
O
LINK OFF output (Not used in this set.)
51
PD2
O
Not used. (Open)
52
ILL-ON
O
Illumination power supply control output
53
VSS
—
Ground
54
DOOR SW
I
DOOR switch input (“L” : close, “H” : open)
55
NCO
—
Not used. (Open)
56
PD6
O
Not used. (Open)
57
BOOT
I
FLASH write mode detection input
58
VCC
—
Power supply pin (+5 V)
59
NC
—
Not used. (Open)
60
TX/FL-SO/LCDDATA
O
LCD driver serial data/FLASH rewriting serial data output
61
SP-SI
I
Digital signal processor spectrum analyzer data input
62
RX
I
FLASH rewriting serial data input
63
SP-SCK
I
Digital signal processor spectrum analyzer data serial clock input
64
LCDCLK
O
LCD driver/serial clock output
65
VSS
—
Ground
66
LCDINH
O
LCD driver inhibit control output
67, 68
VSS
—
Ground
69
LCDCE0
O
LCD chip enable output
70
LCDCE1
O
LCD chip enable output
71
P63
O
Not used. (Open)
72 – 78
P27 – 21
O
Not used. (Open)
79
FL W
O
FLASH write control output
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