Sony CDX-C880 Service Manual ▷ View online
– 29 –
TU10
RV1
AM AUTO SCAN/
STOP LEVEL ADJ
RV2
FM AUTO SCAN/
STOP LEVEL ADJ
RV3
FM STEREO
SEPARATION ADJ
(WIDE)
RV4
FM STEREO
SEPARATION ADJ
(NARROW)
SHUF
SHUF
SHUF
AM RF signal
generator
generator
antenna
terminal
terminal
AM dummy
antenna(50
antenna(50
Ω
)
30
Ω
65 pF
15 pF
set
Adjustment Location : tuner unit (TU10)
–set upper view–
AM Auto Scan/Stop Level Adjustment
Setting :
SOURCE
n MODE button
: AM
FREQUENCY SELECT switch (E model) : AM 10K
Procedure :
1. Set to the test mode. (See page 27.)
2. Push the SOURCE button.
3. Push the MODE button and set to AM.
1. Set to the test mode. (See page 27.)
2. Push the SOURCE button.
3. Push the MODE button and set to AM.
Display
4. Push the preset 3 button.
Display
5. Adjust with the volume RV1 on TU10 so that the “AM”
indication turns to “AM0” indication on the display window.
But, in case of already indicated “AM0”, turn the RV1 so that
put out light “0” indication and adjustment.
But, in case of already indicated “AM0”, turn the RV1 so that
put out light “0” indication and adjustment.
Display
Carrier frequency : 1000 kHz
30% amplitude
modulation by
1 kHz signal
output level
30% amplitude
modulation by
1 kHz signal
output level
: 33 dB (44.7
µ
V)
Adjustment Location : tuner unit (TU10)
– 30 –
4-1. IC PIN DESCRIPTIONS
• IC5 CXP84640-011Q (CD SYSTEM CONTROL) (SERVO BOARD)
• IC5 CXP84640-011Q (CD SYSTEM CONTROL) (SERVO BOARD)
Pin No.
Pin Name
I/O
Pin Description
1 – 5
NCO
—
Not used in this set.
6
FP OPEN
I
Front panel open detection input
7
FP CLOSE
O
Front panel close control output
8
LINKOFF
I
Bus interface link input (Not used in this set.)
9
DRV OE
O
Focus/tracking coil/sled motor control output
10
D SW
I
Down switch input (SW4)
11 – 13
NCO
—
Not used in this set.
14
LM EJ
O
Loading motor control output
15
LM LOD
O
Loading motor control output
16
EMPH O
O
De-emphasis ON/OFF control output
17
CDMON
O
CD mechanism deck power control output
18
CD ON
O
CD power control output
19
A MUT
O
System attenuate control output
20
LD ON
O
Lazer power ON/OFF control output
21
CD RST
O
CD system reset output
22 – 24
—
—
Not used in this set.
25
PH3
I
Not used in this set.
26
TSTIN0
I
Not used in this set.
27
TSTIN1
I
Not used in this set.
28
TST CLV
I
Not used in this set.
29
NCO
—
Not used in this set.
30
RESET
I
System reset input (“L” = Reset)
31
X IN
I
X’tal oscillator input of system clock. (10 MHz)
32
X OUT
O
X’tal oscillator output of system clock. (10 MHz)
33
GND
—
Analog GND
34
XT OUT
O
Not used in this set.
35
XT IN
I
Not used in this set.
36
AVSS
—
A/D converter GND
37
AVREF
I
A/D converter reference voltage input
38
TEP L
I
Not used in this set.
39
TEP H
I
Not used in this set.
40
NCO
—
Not used in this set.
41
PH2
I
Not used in this set.
42
SCLK
O
CD-TEXT data read clock output
43
ESPXQOK
O
XQOK signal output to DRAM controller.
44
ESPSDT
I
Serial data input from DRAM controller.
45
GRSRST
O
Reaet signal output to DRAM controller.
46
GRSCOR
I
Sub-cord sync input from DRAM controller.
47
CD XLAT
O
CD signal process serial latch output
48
TX CLK
O
EEPROM serial clock output
49
TX DATA
O
EEPROM serial data output
50
UNISO
O
Not used in this set.
51
BUS CLK
I/O
Bus system serial clock input/output
52
BUS SI
I
Bus system serial interface input
53
BUS SO
O
Bus system serial interface output
54
F OK
I
Focus OK signal input
55
GFS
I
GFS signal detection input
56
SCOR
O
Sub-cord sync output
57
SENS
I
SENS signal input
58
—
I
Fixed at “H” in this set.
59
CD CKO
O
CD signal process serial clock output
SECTION 4
DIAGRAMS
– 31 –
Pin No.
Pin Name
I/O
Pin Description
60
BU.IN
I
Back-up power detection input
61
BUSON
I
Bus on control input
62
IN SW
I
Disc in switch input (SW1)
63
SELF SW
I
Self switch input (SW2)
64
TX CE
O
EEPROM chip enable output
65
SCK2
O
Sub Q read clock output
66
SI2
I
Sub Q 80 bit, PCM peak and level data 16 bit input
67
CD DATA
O
CD signal process serial data output
68
ESPXWRE
O
Write signal output to DRAM controller.
69
ESPXRDE
O
Read signal output to DRAM controller.
70
ESPXLT
O
Serial data latch output to DRAM controller.
71
ESPXSOE
O
XSOE signal output to DRAM controller.
72
VDD
—
Power supply
73
HIN
I
Fixed at “H” in this set.
74
TEXT.ON/OFF
I
Fixed at “H” in this set.
75
PH1
I
Not used in this set.
76
FBTBSEL
I
Not used in this set.
77
CDOSEL
I
Not used in this set.
78 – 80
—
—
Not used in this set.
– 32 –
• IC501 CXD2548R (DIGITAL SERVO, DIGITAL SIGNAL PROCESSOR) (SERVO BOARD)
Pin No.
Pin Name
I/O
Pin Description
1
SYSM
I
System mute input (Not used.)
2
RMUT1
O
R-ch, “0” detection output. (“H” : ON, “L” : OFF) (Not used.)
3
LMUT2
O
L-ch, “0” detection output. (“H” : ON, “L” : OFF) (Not used.)
4
CKOUT
O
Master clock frequency division output (Not used.)
5
VDD0
—
Digital power supply
6
SBSO
O
Serial output of sub-P to W. (Not used.)
7
EXCK
I
Clock input for SBSO read output. (Not used.)
8
SQCK
I
Clock input for SQSO read output.
9
SQSO
O
SubQ 80 bit, PCM peak and level data 16 bit output.
10
SENS
O
SENS output. Output to CPU.
11
SCLK
I
Clock input for SENS real data read.
12
DATA
I
Serial data input from CPU.
13
XLAT
I
Latch input from CPU. Latch serial data at the falling edge.
14
CLOK
I
Serial data transfer clock input from CPU.
15
XRST
I
System reset (“L” : Reset)
16
ACDT
O
Not used.
17
PWM1
I
External control input of spindle motor.
18
XLON
O
Microcomputer extension interface (Output) (Not used.)
19
SPOA
I
Microcomputer extension interface (Input A) (Not used.)
20
WFCK
O
WFCK (Write Flame Clock) output
21
GTOP
O
GTOP output
22
XUGF
O
XUGF output (Not used.)
23
XPCK
O
XPLCK output (Not used.)
24
GFS
O
GFS output
25
RFCK
O
RFCK output
26
C2PO
O
C2PO output (Not used.)
27
XROF
O
XROF output
28
SCOR
O
“H” output at either detection, sub code sync S0 or S1.
29
MNT0
O
MNT0 output (Not used.)
30
MNT1
O
MNT1 output (Not used.)
31
MNT3
O
MNT3 output (Not used.)
32
VSS1
—
Digital GND
33
DOUT
O
Digital-Out output
34
ATSK
I
For anti-shock.
35
MIRR
O
Mirror signal output (Not used.)
36
DFCT
O
Diffect signal output (Not used.)
37
FOK
O
Focus OK signal output
38
VDD1
—
Digital power supply
39
VPCO1
O
Charge pump output for wideband EFM PLL.
40
VPCO2
O
VCO2 charge pump output for wideband EFM PLL.
41
VCK.I
I
VCO2 oscillator input for wideband EFM PLL.
42
V16M
O
VCO2 oscillator output for wideband EFM PLL.
43
VCTL
I
VCO2 control input for wideband EFM PLL.
44
PCO
O
Charge pump output for master PLL.
45
FILO
O
Filter output for master PLL (slave = digital PLL).
46
FILI
I
Filter input for master PLL.
47
AVSS4
—
Analog GND
48
CLTV
I
VCO control voltage input for master.
49
AVDD4
—
Analog power supply
50
RFAC
I
EFM signal input
51
BIAS
I
Asymmetry circuit constant current input
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