Sony CDX-C8000R / CDX-C8000RX Service Manual ▷ View online
29
29
• IC805 CXD2726Q-4 (DIGITAL SIGNAL PROCESSOR, DIGITAL FILTER, D/A CONVERTER) (DSO BOARD)
Pin No.
Pin Name
I/O
Pin Description
1
DGND
—
Ground terminal (digital system)
2 – 15
T.P
I
Input terminal for the test (fixed at “L”)
16 – 21
TST0 – TST5
I
Input terminal for the test (fixed at “L”)
22 – 24
JPE1 – JPE3
I
External condition jump terminal “H”: condition jump (fixed at “L”)
25
DVDD
—
Power supply terminal (+3.3 V) (digital system)
26
DA1GND
—
Ground terminal (for D/A converter 1) (analog system)
27
DA1LO
O
D/A converter 1 (L-ch side) output terminal
Analog signal output for front side (L-ch side) output in this set
28
DA1VDD
—
Power supply terminal (+3.3 V) (for D/A converter 1) (analog system)
29
DA1RO
O
D/A converter 1 (R-ch side) output terminal
Analog signal output for rear side (L-ch side) output in this set
30
DA1VDD
—
Power supply terminal (+3.3 V) (for D/A converter 1) (analog system)
31
DA1GND
—
Ground terminal (for D/A converter 1) (analog system)
32
ADLVDD
—
Power supply terminal (+3.3 V) (for L-ch side A/D converter) (analog system)
33
ADLGND
—
Ground terminal (for L-ch side A/D converter) (analog system)
34
ADLREF
O
Connected to the bus control for A/D converter (for L-ch side)
35
ADLIN
I
A/D converter (L-ch side) analog input terminal
Tuner and bus audio input signal (L-ch side) in this set
36
DA2GND
—
Ground terminal (for D/A converter 2) (analog system)
37
DA2VDD
—
Power supply terminal (+3.3 V) (for D/A converter 2) (analog system)
38
DA2LO
O
D/A converter 2 (L-ch side) output terminal (Not used.)
39
MCKVDD
—
Power supply terminal (+3.3 V) (for master clock) (analog system)
40
MCKO
O
System clock output terminal (16.9344 MHz)
41
MCKI
I
System clock input terminal (16.9344 MHz)
42
MCKGND
—
Ground terminal (for master clock) (analog system)
43
DA2RO
O
D/A converter 2 (R-ch side) output terminal
Analog signal output for sub woofer output in this set
44
DA2VDD
—
Power supply terminal (+3.3 V) (for D/A converter 2) (analog system)
45
DA2GND
—
Ground terminal (for D/A converter 2) (analog system)
46
ADRIN
I
A/D converter (R-ch side) analog input terminal
Tuner and bus audio input signal (R-ch side) in this set
47
ADRREF
O
Connected to the bus control for A/D converter (for R-ch side)
48
ADRGND
—
Ground terminal (for R-ch side A/D converter) (analog system)
49
ADRVDD
—
Power supply terminal (+3.3 V) (for R-ch side A/D converter) (analog system)
50
DA3GND
—
Ground terminal (for D/A converter 3) (analog system)
51
DA3VDD
—
Power supply terminal (+3.3 V) (for D/A converter 3) (analog system)
52
DA3LO
O
D/A converter 3 (L-ch side) output terminal
Analog signal output for rear side (R-ch side) output in this set
53
DA3GND
—
Power supply terminal (+3.3 V) (for D/A converter 3) (analog system)
54
DA3RO
O
D/A converter 3 (R-ch side) output terminal
Analog signal output for front side (R-ch side) output in this set
55
DA3GND
—
Ground terminal (for D/A converter 3) (analog system)
56
DGND
—
Ground terminal (digital system)
57
SYSRST
I
System reset signal input from the master controller (IC502) “L”: reset
58
BFOT
O
Master clock signal output terminal
59
SCK
I
Serial data transfer clock signal input from the master controller (IC502) and liquid
crystal display drive controller (IC701)
60
REDY
O
Transfer enable signal output to the master controller (IC502)
“L”: transfer prohibition
61
TRDT
O
Serial data output to the master controller (IC502) and liquid crystal display drive
controller (IC701)
62
XLAT
I
Serial data latch pulse input from the master controller (IC502)
Pin No.
Pin Name
I/O
Pin Description
63
RVDT
I
Serial data input from the master controller (IC502)
64
24/23BIT
I
Serial data 24/32 bit slot selection signal input terminal
“L”: 24 bit slot, “H”: 32 bit slot (validity at slave mode) (fixed at “L” in this set)
65
DVDD
—
Power supply terminal (+3.3 V) (digital system)
66
DVSS
—
Ground terminal (digital system)
67 – 69
SO1 – SO3
O
Serial data output terminal (Not used.)
70
SOUT
O
Serial data output terminal (Not used.)
71
SI1
I
Serial data input terminal
72, 73
SI2, SI3
I
Serial data input terminal Not used (fixed at “L”)
74
SIN
I
Serial data input terminal Not used (fixed at “L”)
75
BCK
I
Bit clock signal (2.8224 MHz) input terminal
76
LRCK
I
L/R sampling clock signal (44.1 kHz) input terminal
77
MST/SLV
I
Bit clock (BCK) and L/R sampling clock (LRCK) signal master/slave mode selection
signal input from the master controller (IC502) “L”: master mode, “H”: slave mode
78
DVDD
—
Power supply terminal (+3.3 V) (digital system)
79
PLLGND
—
Ground terminal (PLL system)
80
PLLENA
I
PLL enable signal input terminal Normally: fixed at “L”
81
22 MHz
O
PLL clock signal output terminal (22.5792 MHz) (Not used.)
82
PLLCNT
I
PLL clock output control signal input from the master controller (IC502)
At “L” is input: fixed at “L” is PLCLK (pin ia)
At “H” is input: PLL clock signal output from the PLCLK (pin ia)
83
PLLVDD
—
Power supply terminal (+3.3 V) (PLL system)
84
DGND
—
Ground terminal (digital system)
85 – 94
T.P
I
Input terminal for the test Normally: fixed at “L”
95
DVDD
—
Power supply terminal (+3.3 V) (digital system)
96
DRAMGND
—
Ground terminal (for D-RAM)
97 – 99
T.P
I
Input terminal for the test Normally: fixed at “L”
100
DRAMVDD
—
Power supply terminal (+3.3 V) (for D-RAM)
30
30
04
I-V
CONV.
FOCUS
ERROR
DIGITAL
CLV
SUB
CODE
PROCESS
TRACKING
ERROR
LD
DRIVE
Q101
FOCUS
COIL
DRIVE
RF
EQ
EQ
EFM
DEM
D/A
I/F
RFO
RFAC
LRCK
FE
TE
SE
RFDC
FFDR
FRDR
TFDR
SFDR
SRDR
MDP
TRDR
TE
FE
E
D
B
C
A
F
11
10
PD
4
LD
3
7
6
8
13
14
16
LD
AMP
LD ON
HOLD SW
AGC CONT
22
21
20
5
RF AMP, LD APC,
ERROR AMP
IC1
DIGITAL SERVO,
DIGITAL SIGNAL PROCESSOR
IC501
TRACKING/FOCUS COIL DRIVE
SLED/SPINDLE/LOADING MOTOR DRIVE
IC7
10
11
22
21
TRACKING
COIL
DRIVE
8
9
25
24
SLED
MOTOR
DRIVE
6
7
31
32
32
FOCUS
COIL
TRACKING
COIL
M902
SLED
MOTOR
SPINDLE
MOTOR
DRIVE
12
13
18
M901
SPINDLE
MOTOR
LOADING
MOTOR
DRIVE
5
4
1
2
34
35
M903
LOADING
MOTOR
MUTE 1
MUTE 2
42
43
40
41
38
39
35
52
51
50
61
77
PCMD
79
XTAI
86
BCK
81
SQSO
6
SQCK
7
SCOR
MD2
24
73
XRST 11
DATA 13
DATA 13
XLAT 14
SCLK 17
CLOK 15
SENS 16
SENS 16
GFS 22
FOK 32
FOK 32
LOCK
34
54
SERVO
CTL
X1
10MHz
SW3
(LIMIT)
SW1
(DISC IN)
SW4
(DOWN)
SW2
(SELF)
LM EJ
69
LM LOD
66
SLED –
40
DRIVE OE
70
LD ON
20
HOLD
22
AGC CONT
23
SSTP
11
(KEY BOARD)
OPEN
6
FOK
XIN
XOUT
54
GFS
55
SENS
57
CD CKO
65
SCLK
45
CD XLAT
68
CD DATA
67
CD RST
21
MD2
71
SCOR
64
SCK2
48
SI2
49
LOCK
16M
BCK
LRCK
DATA
46
IN SW
62
D SW
10
SELF SW
63
CD SYSTEM CONTROL
IC5
SYSTEM CONTROL
IC502 (1/3)
BUS CLK 51
A MUT 19
BUS SI 52
BUS SO
SRST
BUS CLK
BUS SI
BUS ON
BUS CHECK
UNI SO
LINK OFF
53
TO DISPLAY
SECTION
1
4
ATT
MDON
CDON
CDON
TO TUNER
SECTION
TO DISPLAY
SECTION
2
BUS ON 61
RESET 30
BU IN 60
S101
(RESET)
HSTX
RESET
1
2
IC503
BU 5V
BATT (H)
CHECK
Q604
BATT (L)
CHECK
BATT
86
RSTX
90
SIRCS 24
BU IN
77
SYS RST
6
BUS ON
14
UNI SO
18
UNI SI
17
UNI CKO
19
EMPH 16
MDON 17
CDON 18
EMPH
97
ATT
5
BATT
10
3
RESET
13
2
BUS ON
CONT
12
9
8
11
1
4
6
BUS INTERFACE
IC601
CLK
DATA
5
4
6
2
1
3
8
7
CN601
BUS
CONTROL IN
Q603
A
C
B
D
E
F
PD
LD
OPTICAL PICKUP
KSS-720A
• Signal path
:CD
31
32
Q601
Q602
Q605
5
TO DISPLAY
SECTION
BATT
BATT
CHECK
Q352
IR
RECEIVE
IC951
CDX-C8000R/C8000RX
3-2. BLOCK DIAGRAM — CD SECTION —
(Page
32)
(Page 31)
(Page 32)
(Page 32)
31
31
04
ANT1
(ANTENNA)
1
10
2
AM ANT
MPX
FL
RL
SR
ADL
19
AM IF
8
AMDET
9
RDS
FM ANT
TUNER UNIT
TUX201
BUF
Q209
MUTE
CONTROL
Q206,207
NOISE
CANCEL
IC202
Q202
Q205
Q208
13
12
11
15
14
20
21
18
31
32
50
56
7
3
SYSTEM CONTROL
IC502 (2/3)
16
20
14
S METER
VSM
MPTH
DAVN
NS MASK
QUALITY
TU ATT
VOL ATT
EXTATT
SCL
SDA
S METER
MP IV
AM
R-CH
AM IF
MPX
38 ACOUTL
35 SWINR
33 AC INLR
34 ACINLF
12
SDA IIC
70 I2CSIO
13
SCL IIC
71 I2CCKO
4
FM AGC
51 FM AGC
17
SDA EEPROM
10 E2PSIO
18
SCL EEPROM
11 E2PCKO
RDS DECODER
IC201
MPX
XO
XI
LVIN
4
5
X101
4.332MHz
9
SDA
SCL 10
MPTH 2
DAVN 8
1
30
SEL
OUT FL
ELECTRONIC VOLUME
IC301
29
OUT RL
25
OUTSWR
55
AMP ON
96
TEL ATT
95
ILL IN
81
ACC IN
73
XIA
BATT
74
XDA
84
TEST
83
PW ON
92
XO
93
XI
113
TU ON
ATT
TO DISPLAY
SECTION
3
TO CD
SECTION
4
Q356
Q358
Q360
Q353
MUTE
CONTROL
Q354, 355
12
5
3
11
22
4
9
7
POWER AMP
IC351
MUTE
STBY
CN101
FL+
FL–
RL+
RL–
TEL MUTE
ILL
ACC
TEST
FR+
13
14
7
15
4
10
2
9
1
12
3
11
COM 8V
FR–
RR+
RR–
5
AMP REM
6
ANT REM
16
BATT
X103
32.768kHz
X104
3.68MHz
ILL
DET
Q113
POWER
CONT.
Q364,366
ACC
DET
DET
Q112
POWER
CONT
Q107-109
Q111
R-CH
BATT
BATT
BATT
TU5V
REG
Q201
TU8V
TU 8V
POWER
CONT
Q203,204
COM8V
CN301
CN302
–2
–1
R
L
SUB OUT
–3
–4
R
L
AUDIO OUT
REAR
R-CH
R-CH
–5
–6
R
L
AUDIO OUT
FRONT
R-CH
–1
–2
R
L
BUS AUDIO IN
R-CH
53
7
SW SHIFT
SW SHIFT
21
POWER
CONT.
Q363,365
52
75
3-3. BLOCK DIAGRAM — TUNER SECTION —
(Page 30)
(Page 32)
CDX-C8000R/C8000RX
32
32
04
BUS SI
BUS CLK
BUS ON
BUS CHECK
LINK OFF
S RST
UNI SO
BUF
IC702
7
6
LCD DRIVER
IC901
100
99
98
85
84
86
CLK
DATA
CE
AMBER
GREEN
DIMMER
RES
LINK OFF
NMI
UNI SI
UNI SO
BUS IN
BUS ON
UNI SCK
60 LCD DATA
64 CLK
66
52
CEI
LCD+B
+6V
ILLON
BATT
33
SP LAT
57
BOOT
SP SI
XTAL
EXTAL
SP SCK
POWER
CONT.
Q703-705
RAM
BACKUP
KEY IN
MATRIX
KEY
ACTIVE
Q701
AD ON
CONT.
Q702
BU5V
AD ON
RE901
ROTALY
ENCODER
BU 5V
BU 5V
FLASH ON
SP LATCH
BOOT
98
61
63
101
38
49
82
50
81
97
SUB SYSTEM CONTROL
IC701
TO CD
SECTION
2
LCD901
2
1
LED
DRIVE
Q771,772
DOOR IND
NOSESW
RAMBU
85
16M
AND
IC804
BCK
LRCK
DATA
MST
4
1
2
82
4
KEY IN1
47
KEY IN0
46
RC IN1
72
KEY ACK
79
ADON
80
REIN0
116
RE IN1
115
RC IN0
48
106
BFOT
58
BCK
75
LRCK
76
SI1
R-CH
R-CH
R-CH
ADL
SR
71
MST/SLV
77
REDY
60
XLAT
62
SYS RST
57
SCK
59
TRDT
61
RVDT
63
29
READY 78
LAT 35
RST
DSP
36
CKO 27
SI 25
SO 26
DAILO 27
DA3RO 54
DA1RO 29
DA3LO 52
DA2RO 43
ADL IN 35
ADR IN 46
MCK0 40
MCK1 41
5
6
2
3
9
8
BUFFER
IC803
DSP
IC805
SYSTEM CONTROL
IC502 (3/3)
IC809
RL
IC807
FL
IC807
X801
16.9MHz
16.9MHz
85
86
X105
18.43MHz
TO TUNER
SECTION
3
TO CD
SECTION
5
J651
(REMOTE IN)
TO CD
SECTION
1
DSPPLL 28
F CH 98
DISC ON IN 76
BEEP 15
FSW IN 65
DSP ON
BATT
+6V
Q101
PLL CNT
82
2
7
4
1
POWER
CONT.
Q102,104
POWER
CONT.
Q406,407
REG
Q402,403
BEEP
DRIVE
Q351
ON/OFF
DRIVE
Q103,105,
Q106
BZ101
110
117
118
IC803
+6V
OUT
RT
VCC
INP
DC/DC
CONV.CONT.
IC302
CD5V
MD6V
CD ON
MD ON
IC504
S102
(NOSE DET)
LED771-773
REG
IC801,Q801
REG
Q802
REG
A 3.3V
REG
Q110
BU5V
BATT
DSP5V
D3.3V
LCD+B
1
3
IC802
Q901
Q902
Q903
(C8000R)
3-4. BLOCK DIAGRAM — DISPLAY SECTION —
(Page 30)
CDX-C8000R/C8000RX
(Page 30)
(Page 30)
(Page 31)
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