Sony CDX-805 Service Manual ▷ View online
– 32 –
• IC Block Diagrams
– MAIN Section –
IC101
CXD2530Q
1 2 3 4 5 6
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
43
42
42
41
40
40
39
38
38
37
36
35
34
33
32
31
31
50
49
49
48
47
47
46
45
44
88
89
89
90
91
91
92
93
93
94
95
96
97
98
99
100
81
82
82
83
84
84
85
86
87
71 70 69 68
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
80 79 78 77 76 75 74 73 72
ASYMMETRY
CORRECTOR
DIGITAL
PLL
CLOCK
GENERATOR
D / A
INTERFACE
DIGITAL CLV
SUB CODE
PROCESSOR
TIMING
LOGIC
CPU
INTERFACE
SERVO
AUTO
SEQUENCER
ERROR
CORRECTOR
16K RAM
DIGITAL OUT
OSC
EFM
DEMODULATOR
TES6
VDD
VSS
EXCK
SBSO
SCOR
WFCK
TES5
EMPH
DOUT
C4M
FSTT
XTSL
MNT0
MNT1
MNT3
XROF
C2PO
RFCK
GFS
XPCK
XUGF
GTOP
VDD
VSS
TES4
BCK
TES3
PCMD
TES9
LRCK
WDCK
ASYE
ASYO
ASYI
ASYI
BIAS
RF
AVDD
CLTV
AVSS
FILI
FILO
PCO
PCO
VCTL
V16M
VCKI
VPCO1
VPCO2
TES1
TES0
LOCK
PWMI
MDP
MDS
VSS
MON
FOK
VDD
SPOD
XLON
SPOB
SPOC
CLKO
SPOA
DATO
XLTO
SEIN
CNIN
XLAT
CLOK
SENS
DATA
SQCK
SQSO
TES2
CKOUT
LMUT
RMUT
VDD
VSS
NC
XRST
VSS
NC
NC
VDD
NC
TES8
XVSS
VSS
XTAI
XTAO
VSS
XVDD
TES7
NC
VDD
NC
NC
VSS
IC202
NM24C16EM8X
IC301
BA6287F
1
2
3
4
OUT1
VM
VCC
FIN
8
7
6
5
GND
OUT2
VREF
RIN
CONTROL LOGIC
TSD
POWER
SAVE
DRIVER
DRIVER
SLAVE ADDRESS
REGISTER &
COMPARATOR
4
6
7
8
5
1
2
2
3
CONTROL
LOGIC
WORD
ADDRESS
COUNTER
COUNTER
X
DECODER
EEPROM
128 x 16 x 8
H.V. GENERATOR
TIMING & CONTROL
START CYCLE
START/
STOP
LOGIC
A0
A1
A1
A2
VSS
D OUT
ACK
D IN
R/W
Y
DECODER
DATA
REGISTER
D OUT
SDA
CK
4
16
LOAD
INC
SCL
NC
VCC
16
4
8
8
DEVICE
ADDRESS
BITS
– 33 –
IC601
AK4321-VF-E2
IC302
BA8272F-E2
1
2
3
4
5
6
7
8
9
10
14
13
12
11
VCC
BUS ON
LINK OFF
CLK OUT
DATA OUT
DATA IN
BUS RESET
BUS DATA
VREF
BUS CLK
GND
BUS ON IN
BUS ON OUT
RESET
RESET
SWITCH
IC402
M5M44400BTP-7
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
21
22
23
24
25
26
SENSE REFRESH AMP
INPUT/OUTPUT
CONTROL SWITCH
CLOCK OSC
COLUMN DECODER
MEMORY CELL
INPUT
BUFFER
OUTPUT
BUFFER
A0–A9
D1
D2
XWE
XRAS
A9
NC
NC
NC
A0
A1
A2
A3
A0–A9
A4
A5
A6
A7
A8
NC
NC
NC
XOE
XCAS
D3
D4
GND
VDD
ADDRESS BUFFER
ROW DECODER
CTF
SCF
CLOCK OSC/DIVIDER
∆Σ
MODULATOR
SERIAL INPUT
INTERFACE
8
×
INTERPOLATOR
DE-EMPHASIS
CONTROL
8
×
INTERPOLATOR
∆Σ
MODULATOR
CTF
SCF
1
2
3
4
5
6
7
8
9
10
20
19 18 17 16 15
14
13
12
11
21
22
23
24
TTL
DZF
VREF
AVSS
AVDD
VCOM
AOUTL
AOUTR
BVDD
DIF1
DIF0
DEM1
CKS
DVDD
DVSS
XTO
XTI
PD
BICK
SDATA
LRCK
SMUTE
DFS
DEMO
IC401
CXD2522Q
VWA
ADDRESS MONITOR
WRITE
BASE
COUNTER
READ
BASE
COUNTER
CPU I/F
SELECTOR
TIMING
GEN.
DSP
I/F
DATA
LINKING
CONTROL
DAC
I/F
DIGITAL
OUT
1 2 3 4
5 6 7 8
9 10
20
19
18
17
16
15
14
13
12
11
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
56
55
54
53
52
51 50 49 48 47
57
58
59
60
61
62
63
64
XWIH
AM4
AM3
AM3
AM2
AM1
AM0
VDD
XQOK
GSCR
SCOR
NC
NC
NC
GRST
XRST
WFCK
DIN
C4M
XROI
RFCK
GTOP
BCKI
VSS
DATI
LRCI
WDCI
TEST
XTAO
XTAI
BCK
DATA
LRCK
DOUT
C176
A3
A2
A1
A0
VDD
A9
XRAS
XWE
D1
D0
D3
D2
XCAS
XOE
A8
A7
A6
A5
A4
OSCE
VSS
SPSL
XEMP
SDTO
XSOE
SCK
SDTI
XLT
XRDE
XWRE
DRAM
I/F
– 34 –
IC502
CXK58257BM-10LL-T6
MEMORY
MATRIX
512X512
ROW
DECODER
BUFFER
1
A14
2
3
4
5
A5
A12
A7
A6
26 A13
25 A8
24
25 A8
24
23 A11
A9
I/O GATE
COLUMN
COLUMN
DECODER
BUFFER
6
A4
7
8
9
10
A0
A3
A2
A1
27
28 VCC
WE
22 OE
21 A10
BUFFER
18 I/O7
17 I/O6
16
17 I/O6
16
I/O4
I/O5
19 I/O8
15
I/O BUFFER
11
12
13
I/O3
I/O1
I/O2
20 CE
14
GND
LEVEL
SHIFT
LEVEL
SHIFT
LEVEL
SHIFT
– 35 –
Pin No.
Pin Name
I/O
Function
4-6.
IC PIN FUNCTON DESCRIPTION
MAIN BOARD
IC201 CXP84332-054Q (SYSTEM CONTROLLER)
1-3
–
O
Not used
4
CH. F
O
5
CH. R
O
6
LOAD2
I
Input of LOAD IN switch
7
LOAD1
I
Input of LOAD OUT switch
8
SENS2
I
Input of sense signal from CXA1992AR (IC11) and CXD2530Q (IC101)
9
LIM. SW
I
Input of limit switch
10
EE. INIT
I
Input of initialize signal from E
2
PROM (IC202)
“H” : Format
11
EE. CLK
O
Output of clock signal to E
2
PROM (IC202)
12
EE. DATA
I/O
Input/output of data signal to E
2
PROM (IC202)
13-19
–
O
Not used
20
SINGLE
I
Selection of single mode
“L” : Single CD playing
21
XRST
O
Output of reset signal to peripheral servo IC
22
FOK
I
Input of focus OK signal form CXA1992AR (IC11) and CXD2530Q (IC101)
23
SENS
I
Input of sense signal from CXA1992AR (IC11) and CXD2530Q (IC101)
24
GFS
I
Input of guard frame sync signal from CXD2530Q (IC101)
25
GRSRST
O
Output of GRSCOR reset pulse to CXD2522Q (IC401)
26
XQOK
O
Output of subcode Q OK pulse to CXD2522Q (IC401)
27
SDIT
I
Input of ESP status signal from CXD2522Q (IC401)
28
XSOE
O
Output of ESP status read enable signal to CXD2522Q (IC401)
29
ESPXLT
O
Output of ESP latch pulse to CXD2522Q (IC401)
30
RST
I
Input of system reset signal
“L” : Reset
31
EXTAL
I
Input of system clock (8 MHz)
32
XTAL
O
Output of system clock (8 MHz)
33
VSS
–
Ground pin
34
TX
–
Not used
35
TEX
–
Not used
36
AVSS
–
Ground pin of A/D converter
37
AVREF
I
Input of A/D converter reference voltage
38
MCK
I
Input of signal for fine adjustment of elevator position
39
EHS
I
Input of elevator height detection voltage (RV202)
40
H. TEMP
I
Input of high temperature detection signal
41
XRDE
O
Output of DRAM read enable signal
42
XWRE
O
Output of DRAM write enable signal
43
A. MUTE
O
Output of audio output mute on/off control signal
“H” : Mute on
44
EMP
O
Output of emphasis mode for disc playing
“L” : on
45
ML
O
Selection of fast speed dubbing
“L” : Fast speed
46
GRSCOR
I
Input of GRSCOR from CXD2522Q (CI401)
47
D/A. RESET
O
Output of reset signal to D/A converter (IC601)
48
SCK
I
Input of serial clock signal from SONY bus interface (IC302)
Output of control
signal to the chucking
motor drive (IC52)
signal to the chucking
motor drive (IC52)
FWD
REV
Brake
CH.F
H
L
H
CH.R
L
H
H
Forward : Load chucking
Reverse: Save
Reverse: Save
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