Sony CDX-757MX (serv.man2) Service Manual ▷ View online
CDX-757MX
29
29
CDX-757MX
MAIN BOARD IC201 HD6432238RWN36TEIV (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
TEST
I
Test mode setting terminal “L”: test mode Not used
2
DECXRST
O
Reset signal output to the CD-ROM/MP3 decoder “L”: reset
3
DECSTBY
O
Standby mode control signal output to the CD-ROM/MP3 decoder “H”: standby
4
FOK
I
Focus OK signal input from the DSP “L”: NG, “H”: OK
5
GFS
I
Guard frame sync signal input from the DSP “L”: NG, “H”: OK
6
SCLK
O
Serial data reading clock signal output to the DSP
7
SENS
I
Internal status signal (sense signal) input from the DSP
8
CDCLK
O
Serial data transfer clock signal output to the DSP
9
CDLAT
O
Serial data latch pulse signal output to the DSP
10
CDDAT
O
Serial data output to the DSP
11
XRST
O
System reset signal output to the DSP “L”: reset
12
CVCC
—
Power supply terminal (+3.3V) (for system)
13
NC
O
Not used
14
VSS
—
Ground terminal
15
XQOK
O
Subcode Q OK pulse signal output to the DSP
16
XRDE
O
Read enable signal output to the DSP
17
XWRE
O
Write enable signal output to the DSP
18
DAC-DATA
O
Mode control data output to the D/A converter
19
DAC-CLK
O
Mode control data transfer clock signal output to the D/A converter
20
DAC-LAT
O
Mode control data latch pulse signal output to the D/A converter
21
ESPSEL
I
ESP mode setting terminal “L”: ESP on (fixed at “L” in this set)
22
TEXTSEL
I
CD text mode setting terminal “L”: CD text on (fixed at “L” in this set)
23
CFSEL
I
Custom file on/off setting terminal “L”: custom file on (fixed at “L” in this set)
24
DOUT SEL
I
Input terminal for digital out on/off setting “L”: digital out on Not used
25
MAG-SW
I
Magazine detect switch input terminal Not used
26
MUTE
O
Audio line muting on/off control signal output terminal “H”: muting on
27, 28
NC
O
Not used
29
CDON
O
D/A convert and servo sections power supply on/off control signal output terminal
“H”: power on
“H”: power on
30
EVON
O
Mechanism deck section power supply on/off control signal output terminal “H”: power on
31
PCTX
O
PC connecting output terminal for UART
32
PCRX
I
PC connecting input terminal for UART
33 to 35
NC
O
Not used
36
ELVF
O
Motor drive signal (elevator up direction) output to the elevator motor drive
37
ELVR
O
Motor drive signal (elevator down direction) output to the elevator motor drive
38
SCOR
I
Subcode sync (S0+S1) detection signal input from the DSP
39
NC
O
Not used
40
GRSCOR
I
Subcode sync (S0+S1) detection signal input from the DSP
41
NC
O
Not used
42
AVSS
—
Ground terminal (for A/D converter)
43 to 49
NCI
I
Not used
50
EHS
I
Elevator height position detection signal input from the elevator height sensor (A/D input)
51
NCI
I
Not used
52
MCK
I
Input of detection signal for the fine adjustment (elevator height (address) adjustment) of elevator
height position (A/D input)
height position (A/D input)
•
IC Pin Function Description
Pin No.
Pin Name
I/O
Description
53
VREF
I
Reference voltage (+3.3V) input terminal (for A/D converter)
54
AVCC
—
Power supply terminal (+3.3V) (for A/D converter)
55, 56
MD0, MD1
I
Setting terminal for the CPU operational mode “H”: single chip mode (fixed at “H” in this set)
57
OSC2
O
Sub system clock output terminal Not used
58
OSC1
I
Sub system clock input terminal Not used (fixed at “L”)
59
RES
I
System reset signal input from the SONY bus interface and reset signal generator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
60
NMI
O
Not used (fixed at “H”)
61
STBY
O
Standby mode control signal output terminal Not used (fixed at “H”)
62
VCC
—
Power supply terminal (+3.3V)
63
XTAL
I
Main system clock input terminal (12.288 MHz)
64
VSS
—
Ground terminal
65
EXTAL
O
Main system clock output terminal (12.288 MHz)
66
FEW
I
Flash memory data write enable signal input terminal
67
MD2
I
Setting terminal for the CPU operational mode “H”: single chip mode (fixed at “H” in this set)
68
FL BOOT
I
Flash memory data write control signal input terminal “L” active
69
FL W
O
Flash memory data write control signal output (connecting FEW (pin yh))
70, 71
NC
O
Not used
72
MGLK-SW
I
Magazine in/out detect switch input terminal “L”: magazine in
73
DECINT
I
Interrupt signal input from the CD-ROM/MP3 decoder
74
NC
O
Not used
75
EJECT
I
Eject switch input terminal “L” active
76
SO
O
Serial data output to the SONY bus interface
77
SI
I
Serial data input from the SONY bus interface
78
SCLK
I
Serial data transfer clock signal input from the SONY bus interface
79
EEDATA
I/O
Two-way data bus with the EEPROM
80
SDA
I/O
I2C interface data input/output with the CD-ROM/MP3 decoder
81
SCL
O
I2C interface data transfer clock signal output to the CD-ROM/MP3 decoder
82
EECLK
O
Serial data transfer clock signal output to the EEPROM
83
NC
O
Not used
84
SQSO
I
Subcode Q data input from the DSP
85
SQCK
O
Subcode Q data reading clock signal output to the DSP
86 to 89
NC
O
Not used
90
R/RW SEL
O
CD-ROM/RW selection signal output terminal “L”: CD-RW, “H”: CD-ROM
91
BUSON
I
Bus on/off control signal input from the SONY bus interface “L”: bus on
92
BUCHK
I
Battery detection signal input terminal “H”: low battery (Normally: “L”)
93, 94
NC
O
Not used
95
LOADF
O
Motor drive signal (load chucking direction) output to the chucking motor drive
96
LOADR
O
Motor drive signal (save direction) output to the chucking motor drive
97
SINGLE
I
Setting terminal for the single disc/multiple discs mode
“L”: single disc mode, “H”: multiple discs mode (fixed at “H” in this set)
“L”: single disc mode, “H”: multiple discs mode (fixed at “H” in this set)
98
LOAD SW
I
Chucking end detect switch input terminal
“L”: When completion of the disc chucking operation
“L”: When completion of the disc chucking operation
99
SAVE SW
I
Save end detect switch input terminal
“L”: When completion of the disc save operation
“L”: When completion of the disc save operation
100
LIM SW
I
Sled limit in detect switch input terminal
“L”: When the optical pick-up is inner position
“L”: When the optical pick-up is inner position
CDX-757MX
30
30
CDX-757MX
JACK BOARD
(COMPONENT SIDE)
1-684-650-
12
(12)
JACK FLEXIBLE BOARD
MAIN BOARD
CN301
B
JACK BOARD
(CONDUCTOR SIDE)
1-684-650-
12
(12)
4
2
1
5
3
6
7
8
5
4
8
7
6
2
1
3
CONTROL
(FOR SONY BUS)
AUDIO OUT
L
R
CN901
1
2
3
4
5
6
7
8
9
10
A
B
C
D
(Page 24)
6-11. PRINTED WIRING BOARDS – JACK Board –
•
See page 21 for Circuit Boards Location.
31
CDX-757MX
6-12. SCHEMATIC DIAGRAM – JACK Board –
C904
D901
FB901
FB902
FB903
C901
C902
TP906
TP907
TP908
TP909
TP905
TP904
TP903
TP902
TP901
CN901
CNJ901
PS901
100p
STZ6.8N
-T146
0.001
0.1
13P
5A
32V
RST
CLK
DATA
BUSON
GND
SIRCS
B.UP
L
R
CLK
RST
DATA
BUSON
GND
GND
GND
B.UP
B.UP
B.UP
LCH
AGND
RCH
NC
JACK
FLEXIBLE
BOARD
CONTROL
L
R
AUDIO OUT
(FOR SONY BUS)
(Page 27)
32
CDX-757MX
•
Waveforms
Approx.
250 mVp-p
250 mVp-p
Approx.
100 mVp-p
100 mVp-p
1.4
±
0.3 Vp-p
3.8
µ
s
2 Vp-p
22.7
µ
s
4.5 Vp-p
22.7
µ
s
4.5 Vp-p
22.7
µ
s
4.5 Vp-p
472 ns
4.5 Vp-p
472 ns
4.5 Vp-p
472 ns
4.5 Vp-p
59.1 ns
5 Vp-p
59.1 ns
5 Vp-p
59.1 ns
5 Vp-p
81.4 ns
2.2 Vp-p
– RF Board –
– MAIN Board –
1
IC101
qh
(FE)
50 mV/DIV, 500 ns/DIV
2
IC101
qk
(TE)
100 mV/DIV, 500 ns/DIV
3
IC101
qg
(RFAC)
500 mV/DIV, 500 ns/DIV
qj
IC601
ys
(X1)
1 V/DIV, 20 ns/DIV
qk
IC201
yg
(EXTAL)
500 mV/DIV, 50 ns/DIV
ql
IC501
1
(BCK)
1 V/DIV, 200 ns/DIV
w;
IC501
3
(LRCK)
2 V/DIV, 10
µ
s/DIV
wa
IC501
qh
(SCK)
1 V/DIV, 20 ns/DIV
qa
IC101
rd
(MDP)
500 mV/DIV, 1
µ
s/DIV
qs
IC101
ih
(LRCK),
ij
(LRCKI)
2 V/DIV, 10
µ
s/DIV
qd
IC101
o;
(BCK),
oa
(BCKI)
1 V/DIV, 200 ns/DIV
qf
IC101
of
(XTAO)
1 V/DIV, 20 ns/DIV
qg
IC601
qd
(BCKIA)
1 V/DIV, 200 ns/DIV
qh
IC601
qf
(LRCKIA)
2 V/DIV, 10
µ
s/DIV
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